Patents by Inventor Kenichi Shigenami

Kenichi Shigenami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7351068
    Abstract: A semiconductor device includes a first plate member having a circuit surface on which a circuit is provided, a second plate member having a circuit surface on which a circuit is provided, a plurality of first flat plates disposed on the circuit surface of the first plate member, a first communicating section disposed on the circuit surface of the first plate member, a plurality of second flat plates disposed on the circuit surface of the second plate member, and a second communicating section disposed on the circuit surface of the second plate member. The first plate member and the second plate member are arranged so that a surface of the first plate member opposite to the circuit surface faces a surface of the second plate member opposite to the circuit surface.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: April 1, 2008
    Assignee: Sony Corporation
    Inventors: Shunichi Sukegawa, Kenichi Shigenami, Mamoru Kudo
  • Publication number: 20070184677
    Abstract: A semiconductor device includes a first plate member having a circuit surface on which a circuit is provided, a second plate member having a circuit surface on which a circuit is provided, a plurality of first flat plates disposed on the circuit surface of the first plate member, a first communicating section disposed on the circuit surface of the first plate member, a plurality of second flat plates disposed on the circuit surface of the second plate member, and a second communicating section disposed on the circuit surface of the second plate member. The first plate member and the second plate member are arranged so that a surface of the first plate member opposite to the circuit surface faces a surface of the second plate member opposite to the circuit surface.
    Type: Application
    Filed: January 26, 2007
    Publication date: August 9, 2007
    Applicant: SONY CORPORATION
    Inventors: Shunichi SUKEGAWA, Kenichi Shigenami, Mamoru Kudo
  • Publication number: 20070120569
    Abstract: A communication semiconductor chip performs wireless communication with another communication semiconductor chip. The semiconductor chip includes a communication module and a control unit. The communication module performs the wireless communication with another communication semiconductor chip and has a receiving circuit for receiving data. The control unit supplies a reference voltage to the receiving circuit and performs a calibration operation on the reference voltage.
    Type: Application
    Filed: October 31, 2006
    Publication date: May 31, 2007
    Applicant: Sony Corporation
    Inventors: Shunichi Sukegawa, Takeo Sekino, Kenichi Shigenami, Shinichi Toi, Tatsuo Shimizu
  • Publication number: 20070001270
    Abstract: A communication board mounted on an electronic device includes a plurality of antennas configured to transmit and/or receive a signal by electromagnetic induction, where each of the plurality of antennas is provided on a substrate, as a coil-shaped pattern, a semiconductor chip mounted on the substrate, the semiconductor chip including at least one of a transmission circuit which transmits a signal to the antenna and a reception circuit which receives a signal transmitted from the antenna, and an input-and-output end that is connected to the semiconductor chip via a wiring layer provided on the substrate and an electronic circuit of the electronic device. The communication board communicates with a communication board mounted on another electronic device via the antenna by electromagnetic induction.
    Type: Application
    Filed: June 23, 2006
    Publication date: January 4, 2007
    Applicant: SONY CORPORATION
    Inventors: Shunichi Sukegawa, Takeo Sekino, Kenichi Shigenami, Shinichi Toi, Tatsuo Shimizu
  • Patent number: 7027347
    Abstract: A semiconductor memory device for improving the utilization of a shared data bus and the data transfer rate in a multi-bank DRAM and realizing high speed data accessing without increasing a scale of a control circuit, wherein the multi-bank DRAM has memory banks provided with an address register for holding a write address, a data register for holding write data, an address matching detection circuit for detecting whether an address held in the address register matches with an address input this time, and when reading is performed continuously from writing on the same address of the same memory bank, reading is not performed on a memory cell specified by a read address and data held in the data register is output as read data, so that memory accessing made continuously to the same address can be performed at a high speed.
    Type: Grant
    Filed: January 2, 2004
    Date of Patent: April 11, 2006
    Assignee: Sony Corporation
    Inventors: Kenichi Shigenami, Shunichi Sukegawa
  • Patent number: 7012831
    Abstract: A semiconductor memory device for realizing high speed writing while maintaining the credibility of write data, wherein a write gate is provided between a bit line and an input/output data line of a memory cell array, the write gate becomes open when a selected word line becomes an activation state and a write signal set to the input/output data line in accordance with write data is applied to the selected bit line via the write gate when writing, so that writing of data to a selected memory cell can be performed immediately after activating the selected word line when writing, and writing to the selected memory cell can be performed in parallel with reading and refreshing of non-selected memory cells, and consequently, a time for storing charges to the selected memory cell can be sufficiently secured and writing at a high speed can be realized.
    Type: Grant
    Filed: January 2, 2004
    Date of Patent: March 14, 2006
    Assignee: Sony Corporation
    Inventors: Kenichi Shigenami, Shunichi Sukegawa
  • Publication number: 20060043585
    Abstract: A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a plurality of first communication units for transmitting and receiving signals to and from a second substrate, input-output circuits disposed on the first region or the second region, the input-out circuits corresponding to the first communication units, and a control circuit for controlling input to and output from the input-output circuits disposed on the first region or the second region of the first substrate. Each of the input-output circuits includes an output circuit for outputting a signal to a second communication unit of the second substrate corresponding to the first communication unit and an input unit for receiving a signal sent from the corresponding second communication unit.
    Type: Application
    Filed: August 12, 2005
    Publication date: March 2, 2006
    Applicant: Sony Corporation
    Inventors: Shunichi Sukegawa, Takeo Sekino, Kenichi Shigenami, Shinichi Toi, Tatsuo Shimizu
  • Publication number: 20040190363
    Abstract: A semiconductor memory device for improving the utilization of a shared data bus and the data transfer rate in a multi-bank DRAM and realizing high speed data accessing without increasing a scale of a control circuit, wherein the multi-bank DRAM has memory banks provided with an address register for holding a write address, a data register for holding write data, an address matching detection circuit for detecting whether an address held in the address register matches with an address input this time, and when reading is performed continuously from writing on the same address of the same memory bank, reading is not performed on a memory cell specified by a read address and data held in the data register is output as read data, so that memory accessing made continuously to the same address can be performed at a high speed.
    Type: Application
    Filed: January 2, 2004
    Publication date: September 30, 2004
    Inventors: Kenichi Shigenami, Shunichi Sukegawa
  • Publication number: 20040190326
    Abstract: A semiconductor memory device for realizing high speed writing while maintaining credibility of write data, wherein a write gate is provided between a bit line and an input/output data line of a memory cell array, the write gate becomes open when a selected word line becomes an activation state and a write signal set to the input/output data line in accordance with write data is applied to the selected bit line via the write gate when writing, so that writing of data to a selected memory cell can be performed immediately after activating the selected word line when writing, and writing to the selected memory cell can be performed in parallel with reading and refreshing of non-selected memory cells, consequently, a time for storing charges to the selected memory cell can be sufficiently secured and writing at a high speed can be realized.
    Type: Application
    Filed: January 2, 2004
    Publication date: September 30, 2004
    Inventors: Kenichi Shigenami, Shunichi Sukegawa