Patents by Inventor Kenichi Shoji
Kenichi Shoji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12272952Abstract: A control system is provided for a power conversion system having a power converter that controls a virtual synchronous generator simulating a synchronous generator and interconnected to a power grid. The control system has a virtual synchronous impedance compensation block inputting an output current detection value of the power converter and a set voltage amplitude command value, simulating a voltage drop due to a virtual synchronous impedance, and calculating an output voltage command value and an internal induced voltage according to the simulated voltage drop; a virtual synchronous generator model determining an angular frequency simulating the synchronous generator; and a PCS output voltage control unit performing control so that an output voltage of the power conversion system coincides with the output voltage command value calculated by the virtual synchronous impedance compensation block.Type: GrantFiled: August 6, 2020Date of Patent: April 8, 2025Assignees: TOKYO ELECTRIC POWER COMPANY HOLDINGS, INCORPORATED, MEIDENSHA CORPORATIONInventors: Kenichi Suzuki, Naoto Maeda, Jun Takami, Ryota Samejima, Hideki Noda, Jun Isoo, Kazu Shoji
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Patent number: 10332795Abstract: It is to provide a manufacturing method of a semiconductor device including the following steps of: preparing a semiconductor substrate having a silicon nitride film on the rear surface; forming an interlayer insulating film having a via hole on the main surface of the semiconductor substrate; and forming a via-fill selectively within the via hole. The method further includes the steps of: performing the wafer rear surface cleaning to expose the surface of the silicon nitride film formed on the rear surface of the semiconductor substrate; and thereafter, forming a photoresist film made of chemical amplification type resist on the interlayer insulating film and the via-fill over the main surface of the semiconductor substrate, in which the semiconductor substrate is stored in an atmosphere with the ammonium ion concentration of 1000 ?g/m3 and less.Type: GrantFiled: August 7, 2017Date of Patent: June 25, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kiyoshi Maeshima, Kotaro Horikoshi, Katsuhiko Hotta, Toshiyuki Takahashi, Hironori Ochi, Kenichi Shoji
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Publication number: 20170358489Abstract: It is to provide a manufacturing method of a semiconductor device including the following steps of: preparing a semiconductor substrate having a silicon nitride film on the rear surface; forming an interlayer insulating film having a via hole on the main surface of the semiconductor substrate; and forming a via-fill selectively within the via hole. The method further includes the steps of: performing the wafer rear surface cleaning to expose the surface of the silicon nitride film formed on the rear surface of the semiconductor substrate; and thereafter, forming a photoresist film made of chemical amplification type resist on the interlayer insulating film and the via-fill over the main surface of the semiconductor substrate, in which the semiconductor substrate is stored in an atmosphere with the ammonium ion concentration of 1000 ?g/m3 and less.Type: ApplicationFiled: August 7, 2017Publication date: December 14, 2017Inventors: Kiyoshi MAESHIMA, Kotaro HORIKOSHI, Katsuhiko HOTTA, Toshiyuki TAKAHASHI, Hironori OCHI, Kenichi SHOJI
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Patent number: 9761487Abstract: It is to provide a manufacturing method of a semiconductor device including the following step of: preparing a semiconductor substrate having a silicon nitride film on the rear surface; forming an interlayer insulating film having a via hole on the main surface of the semiconductor substrate; and forming a via-fill selectively within the via hole. The method further includes the steps of: performing the wafer rear surface cleaning to expose the surface of the silicon nitride film formed on the rear surface of the semiconductor substrate; and thereafter, forming a photoresist film made of chemical amplification type resist on the interlayer insulating film and the via-fill over the main surface of the semiconductor substrate, in which the semiconductor substrate is stored in an atmosphere with the ammonium ion concentration of 1000 ?g/m3 and less.Type: GrantFiled: May 5, 2016Date of Patent: September 12, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kiyoshi Maeshima, Kotaro Horikoshi, Katsuhiko Hotta, Toshiyuki Takahashi, Hironori Ochi, Kenichi Shoji
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Publication number: 20160365278Abstract: It is to provide a manufacturing method of a semiconductor device including the following step of: preparing a semiconductor substrate having a silicon nitride film on the rear surface; forming an interlayer insulating film having a via hole on the main surface of the semiconductor substrate; and forming a via-fill selectively within the via hole. The method further includes the steps of: performing the wafer rear surface cleaning to expose the surface of the silicon nitride film formed on the rear surface of the semiconductor substrate; and thereafter, forming a photoresist film made of chemical amplification type resist on the interlayer insulating film and the via-fill over the main surface of the semiconductor substrate, in which the semiconductor substrate is stored in an atmosphere with the ammonium ion concentration of 1000 ?g/m3 and less.Type: ApplicationFiled: May 5, 2016Publication date: December 15, 2016Inventors: Kiyoshi MAESHIMA, Kotaro HORIKOSHI, Katsuhiko HOTTA, Toshiyuki TAKAHASHI, Hironori OCHI, Kenichi SHOJI
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Publication number: 20150255287Abstract: To improve characteristics of a semiconductor device. An element isolation region is etched by using a photoresist film as a mask, and thereby a p-type well that is a layer under the element isolation region is exposed. Thereafter, deposit over a surface of the photoresist film is etched. Then, a source region is formed by implanting impurity ions into the exposed p-type well by using the photoresist film as a mask, and thereafter, the photoresist film is removed. Thereby, it is possible to prevent a hardened layer from being formed due to injection of impurity ions into the deposit over the surface of the photoresist film. As a result, it is possible to suppress a popping phenomenon when the photoresist film is removed, so that it is possible to prevent a pattern of a gate and the like from being broken.Type: ApplicationFiled: March 6, 2015Publication date: September 10, 2015Inventors: Kenichi SHOJI, Yoshinori KONDA, Yuki OTA, Keiji OKAMOTO, Yuichi SUZUKI, Shutaro TSUCHIMOCHI, Kengo MATSUMOTO, Kazuyuki OZEKI
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Patent number: 6458602Abstract: According to the invention of the present application, for providing an etching technique for a wiring layer capable of decreasing the degradation of characteristics of a ferroelectric film in FeRAM, a wiring material (LI wiring 18, Al wiring 30) connected with an electrode layer of a ferroelectric film 11 (lower electrode 10, upper electrode 12) is fabricated by dry etching using inducely coupled plasma upon forming the wiring layer and, successively, applied with an asher treatment at a temperature of 300° C. or higher by using inducely coupled plasma while introducing a gas mixture, for example, of O2+CF4+H2O.Type: GrantFiled: July 23, 2001Date of Patent: October 1, 2002Assignee: Hitachi, Ltd.Inventors: Takashi Yunogami, Kenichi Shoji
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Patent number: 6407701Abstract: In the GPS receiver, GPS solutions are calculated by performing GPS measurement using a Kalman filter. The GPS receiver is provided with a computing system which calculates 2DRMS according to an equation: 2DRMS=2×{square root over ((&sgr;H—Kalman+L )2+L +(HDOP×&sgr;UERE+L )2+L )} wherein, &sgr;H_Kalman represents a horizontal component of an estimate error obtained from a diagonal in an error covariance matrix calculated in a mathematical process of the Kalman filter, HDOP represents a horizontal dilution of precision, and &sgr;UERE is a user equivalent range error.Type: GrantFiled: March 23, 2001Date of Patent: June 18, 2002Assignee: Clarion Co., Ltd.Inventors: Mutsumi Ito, Kenichi Shoji
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Publication number: 20010024172Abstract: In the GPS receiver, GPS solutions are calculated by performing GPS measurement using a Kalman filter.Type: ApplicationFiled: March 23, 2001Publication date: September 27, 2001Inventors: Mutsumi Ito, Kenichi Shoji
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Patent number: 5323031Abstract: To eliminate misfit dislocation occurring in a hetero-interface and to provide a bipolar transistor capable of a high speed operation, the bipolar transistor is configured such that the energy band gap is progressively narrowing from part of an emitter layer towards part of a collector layer through a base layer.Type: GrantFiled: March 19, 1992Date of Patent: June 21, 1994Assignee: Hitachi, Ltd.Inventors: Kenichi Shoji, Akira Fukami, Takahiro Nagano