Abstract: The present invention provides an oily solid cosmetic having excellent fixability to the skin, high clarity of application color, and including a powder of a base material that is conspicuous on the skin without whitening. The oily solid cosmetic of the present invention is configured to include a cosmetic base material obtained by mixing a powder (A) and an oily agent (B), and a low viscous liquid oil (C) that is not volatile at normal temperature for rendering muddy the cosmetic base material.

Abstract: To cool field winding from its inner peripheral side and increase an insulation performance, salient-pole rotor (3) has rotor yoke (12) provided along rotation shaft (11), magnetic cores (13) protruding outward in radial direction from outer peripheral portion of rotor yoke (12) and arranged at regular intervals in circumferential direction, magnetic head (14) provided at radial direction outer side of magnetic core (13), and field winding (15) wound around outer peripheral surface of magnetic core (13) between rotor yoke (12) and magnetic head (14). And, insulating structure of ventilation path of salient-pole rotor (3) has ventilation groove (15a) opening to inner peripheral surface of field winding (15) and penetrating field winding (15) in radial direction, ventilation hole (14a) penetrating magnetic head (14) in radial direction and communicating with ventilation groove (15a), and stepped portion (15b) formed at portion, at magnetic head (14) side, of ventilation groove (15a).

Abstract: To cool field winding from its inner peripheral side and increase an insulation performance, salient-pole rotor (3) has rotor yoke (12) provided along rotation shaft (11), magnetic cores (13) protruding outward in radial direction from outer peripheral portion of rotor yoke (12) and arranged at regular intervals in circumferential direction, magnetic head (14) provided at radial direction outer side of magnetic core (13), and field winding (15) wound around outer peripheral surface of magnetic core (13) between rotor yoke (12) and magnetic head (14). And, insulating structure of ventilation path of salient-pole rotor (3) has ventilation groove (15a) opening to inner peripheral surface of field winding (15) and penetrating field winding (15) in radial direction, ventilation hole (14a) penetrating magnetic head (14) in radial direction and communicating with ventilation groove (15a), and stepped portion (15b) formed at portion, at magnetic head (14) side, of ventilation groove (15a).

Abstract: There is provided a nonvolatile semiconductor storage device less subject to variances of electric characteristics among memory cells. A floating gate electrode provided on a substrate is made of two or more materials different in carrier trapping efficiency so as to accumulate carriers and thereby store data in the floating gate electrode. Thus a region without so large changes of the threshold voltage is produced, and the portion with a small change is used as the margin for circuit operations, thereby to eliminate variances among cells and realize high-speed operations.

Abstract: There is provided a nonvolatile semiconductor storage device less subject to variances of electric characteristics among memory cells. A floating gate electrode provided on a substrate is made of two or more materials different in carrier trapping efficiency so as to accumulate carriers and thereby store data in the floating gate electrode. Thus a region without so large changes of the threshold voltage is produced, and the portion with a small change is used as the margin for circuit operations, thereby to eliminate variances among cells and realize high-speed operations.

Abstract: There is provided a nonvolatile semiconductor storage device less subject to variances of electric characteristics among memory cells. A floating gate electrode provided on a substrate is made of two or more materials different in carrier trapping efficiency so as to accumulate carriers and thereby store data in the floating gate electrode. Thus a region without so large changes of the threshold voltage is produced, and the portion with a small change is used as the margin for circuit operations, thereby to eliminate variances among cells and realize high-speed operations.

Abstract: Provided are a memory device capable of accurately reading out data, a method of manufacturing the same, and an integrated circuit. A first control electrode substantially faces a second control electrode with a conduction region and a storage region in between. At the time of “the reading of data”, an electric potential is applied to the first control electrode. During “the reading of data”, a change in an electric potential between the conduction region and the storage region is prevented, and therefore, unintentional writing or erasing of information is prevented, so that written information can be accurately read out.

Abstract: Provided are a memory device capable of accurately reading out data, a method of manufacturing the same, and an integrated circuit. A first control electrode substantially faces a second control electrode with a conduction region and a storage region in between. At the time of “the reading of data”, an electric potential is applied to the first control electrode. During “the reading of data”, a change in an electric potential between the conduction region and the storage region is prevented, and therefore, unintentional writing or erasing of information is prevented, so that written information can be accurately read out.

Abstract: There is provided a nonvolatile semiconductor storage device less subject to variances of electric characteristics among memory cells. A floating gate electrode provided on a substrate is made of two or more materials different in carrier trapping efficiency so as to accumulate carriers and thereby store data in the floating gate electrode. Thus a region without so large changes of the threshold voltage is produced, and the portion with a small change is used as the margin for circuit operations, thereby to eliminate variances among cells and realize high-speed operations.

Abstract: Provided are a memory device capable of accurately reading out data, a method of manufacturing the same, and an integrated circuit. A first control electrode substantially faces a second control electrode with a conduction region and a storage region in between. At the time of “the reading of data”, an electric potential is applied to the first control electrode. During “the reading of data”, a change in an electric potential between the conduction region and the storage region is prevented, and therefore, unintentional writing or erasing of information is prevented, so that written information can be accurately read out.

Abstract: Methods for fabricating memory devices having a multi-dot floating gate ensuring a desirable crystallization of a semiconductor film without ruining the flatness of the surface of the polycrystallized silicon layer and a tunnel oxide film, allowing desirable semiconductor dots to be produced, and allowing production of the memory devices having a multi-dot floating gate with ease and at low costs even when a substrate is made of glass or plastic.

Abstract: A memory device for storing information includes a conductive layer functioning as a current passage, an information storing section, the information storing section comprising at least two quantum dot groups, including a plurality of quantum dots, and a plurality of barrier layers, the barrier layers confining charges in the quantum dots, the energy level localized in a quantum dot group nearer the conductive layer being higher than the energy level localized in another quantum dot group distant from the conductive layer, and a control electrode provided on the information storing section, on the opposite side from the conductive layer. Pulse voltages having different widths and different heights are applied between the conductive layer and the information storing section thereby transferring charge from the conductive layer and accumulating charge in different quantum dot groups in response to the widths and heights to store the information.

Abstract: A novel quantum dot-tunnel device having a revolutionarily faster processing speed and higher processing precision than conventional computer computation, which device has an array consisting of a large number of quantum dots which confine electrons three-dimensionally, with the coupling among quantum dots, that is, the tunnel transition probability, being defined by controlling the positional relationship and the shape of the quantum dots in accordance with an algorithm of predetermined information processing, so that the algorithm is expressed in solid state rather than by a conventional computer program. The electron transition among quantum dots occurs instantaneously and wave mechanically with a strict precision, and the results of the information processing are expressed as a spatial distribution of electrons over the plurality of quantum dots.

Abstract: A novel quantum dot-tunnel device having a revolutionarily faster processing speed and higher processing precision than conventional computer computation, which device has an array consisting of a large number of quantum dots which confine electrons three-dimensionally, with the coupling among quantum dots, that is, the tunnel transition probability, being defined by controlling the positional relationship and the shape of the quantum dots in accordance with an algorithm of predetermined information processing, so that the algorithm is expressed in solid state rather than by a conventional computer program. The electron transition among quantum dots occurs instantaneously and wave mechanically with a strict precision, and the results of the information processing are expressed as a spatial distribution of electrons over the plurality of quantum dots.

Abstract: A semiconductor device or a hot electron transistor being constructed such that an InAs base layer is sandwiched between a GaSb emitter barrier layer and a GaInAsSb-system collector barrier layer, which results in preventing hot electrons of unnecessarily high energy from being injected into the collector and an avalanche current from being generated, thereby making it possible to improve the saturation characteristics of the device.

Abstract: A heterojunction type bi-polar transistor which has a heterojunction in the boundary between an intrinsic base region and an external base region to thereby eliminate the periphery effect and accordingly obtain a high current amplification factor.