Abstract: The storage regions under command of a storage controller can be simply enabled and disabled to access to by automatically registering connected host computers. Such system can be achieved by taking a step of acquiring N_Port_Name information included in a login frame from the host computers, and a step of displaying a table of access right of host computers to a logical unit under command of storage controller. A security table for the storage controller can be generated by supervisor's setting the access enable/disable flag information.

Abstract: The storage controlling apparatus has a function for setting each of a plurality of ports in a controller for the current controller or for the standby controller, so that one port is switched to the other in a controller in case an error occurs in a controller or in a port. When in a normal operation, both of the controllers can be operated so as to improve the performance of the apparatus.

Abstract: According to the invention, techniques for detecting and recovering from errors occurring in disk drive subsystems having a controller and drive units connected by a fiber channel loop. Specific embodiments can provide storage subsystems, methods and apparatus for use in information processing environments, for example. Embodiments can determine when each drive is disconnected from the loop in the external storage subsystem structured by using the FC Loop, and thereupon, the FC Loop can be controlled by bridging the communication path using the PBC so that the loop is not broken.

Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.

Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.

Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.

Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.

Abstract: A semiconductor storage device transfers data with an information processing device and includes a non-volatile semiconductor memory in which data is electrically re-writable, a volatile semiconductor memory connected to the non-volatile memory and temporarily storing data of the non-volatile semiconductor memory, and a CPU connected to the volatile semiconductor memory and the non-volatile semiconductor memory. The CPU controls the transfer of data among the non-volatile memory, the volatile memory and the CPU. The CPU also transfers data with the information processing device in accordance with a fixed-length form for data. When an access from the CPU to the volatile semiconductor makes a miss hit (i.e., misses), the CPU accesses the non-volatile semiconductor memory. When a failure is generated in the non-volatile semiconductor memory or when a predicted service life of the non-volatile semiconductor memory is elapsed, the non-volatile semiconductor memory can be substituted by an alternate memory.

Abstract: A semiconductor storage device is connected to at least one magnetic storage device. The input and output of data is made between the semiconductor storage device and an information processing device.