Patents by Inventor Kenichi TANAMACHI

Kenichi TANAMACHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device, semiconductor device testing method, and data processing system
    Patent number: 8498831
    Abstract: To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: July 30, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Akira Ide, Hideyuki Yoko, Kayoko Shibata, Kenichi Tanamachi, Takanori Eguchi, Yasuyuki Shigezane, Naoki Ogawa, Kazuo Hidaka
  • Semiconductor device, semiconductor device testing method, and data processing system
    Publication number: 20110093224
    Abstract: To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal.
    Type: Application
    Filed: October 8, 2010
    Publication date: April 21, 2011
    Applicant: Elpida Memory, Inc.
    Inventors: Akira Ide, Hideyuki Yoko, Kayoko Shibata, Kenichi Tanamachi, Takanori Eguchi, Yasuyuki Shigezane, Naoki Ogawa, Kazuo Hidaka
  • INITIALIZING CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE HAVING BANK ACTIVE CONTROL CIRCUIT
    Publication number: 20090113157
    Abstract: An initializing circuit initializing a semiconductor memory device includes a command generating circuit generating a mode register set command in response to a reset command signal, a mode register set control circuit producing a reset signal in response to the mode register set command, and a bank active control circuit resetting the semiconductor memory device by generating an all-bank precharge command in response to the reset signal.
    Type: Application
    Filed: October 24, 2008
    Publication date: April 30, 2009
    Applicant: Elpida Memory, Inc.
    Inventors: Shinichi MIYATAKE, Kenichi TANAMACHI