Patents by Inventor Kenichi Tokano
Kenichi Tokano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8431992Abstract: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.Type: GrantFiled: February 8, 2011Date of Patent: April 30, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kenichi Tokano, Tetsuo Matsuda, Wataru Saito
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Publication number: 20110133278Abstract: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.Type: ApplicationFiled: February 8, 2011Publication date: June 9, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Kenichi TOKANO, Tetsuo Matsuda, Wataru Saito
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Patent number: 7936015Abstract: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.Type: GrantFiled: August 18, 2009Date of Patent: May 3, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kenichi Tokano, Tetsuo Matsuda, Wataru Saito
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Patent number: 7898031Abstract: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.Type: GrantFiled: June 23, 2010Date of Patent: March 1, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kenichi Tokano, Tetsuo Matsuda, Wataru Saito
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Publication number: 20100258854Abstract: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.Type: ApplicationFiled: June 23, 2010Publication date: October 14, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Kenichi TOKANO, Tetsuo Matsuda, Wataru Saito
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Patent number: 7714385Abstract: A semiconductor device, including a first semiconductor layer of the first conductivity type having a plurality of trenches formed therein. A second semiconductor layer of the second conductivity type composed of an epitaxial layer is buried in the trenches in the first semiconductor layer. The trench has surface orientations including a surface orientation of a sidewall at an upper stage made slower in epitaxial growth speed than a surface orientation of a sidewall at a lower stage.Type: GrantFiled: December 22, 2006Date of Patent: May 11, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Kenichi Tokano, Hiroyuki Sugaya
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Publication number: 20090302373Abstract: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.Type: ApplicationFiled: August 18, 2009Publication date: December 10, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Kenichi TOKANO, Tetsuo Matsuda, Wataru Saito
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Patent number: 7595530Abstract: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.Type: GrantFiled: March 1, 2006Date of Patent: September 29, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Kenichi Tokano, Tetsuo Matsuda, Wataru Saito
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Patent number: 7531871Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.Type: GrantFiled: December 5, 2005Date of Patent: May 12, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Ichiro Omura, Wataru Saito, Tsuneo Ogura, Hiromichi Ohashi, Yoshihiko Saito, Kenichi Tokano
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Patent number: 7488993Abstract: A semiconductor device, includes: a semiconductor substrate of 100 micrometers or less in thickness; an electrode pattern formed above the semiconductor substrate; and an insulation film of 50 micrometers or greater in thickness residing on parts of the upper surface side of the semiconductor substrate other than at least on the electrode pattern.Type: GrantFiled: February 28, 2005Date of Patent: February 10, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Kenichi Tokano, Motoshige Kobayashi, Kazuyuki Saito
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Patent number: 7423315Abstract: The present application provides a semiconductor device including a first-conductivity type semiconductor substrate, a pillar structure portion formed on the first-conductivity type semiconductor substrate and formed of five semiconductor pillar layers arranged in one direction parallel to a main surface of the first-conductivity type semiconductor substrate, and isolation insulating portions formed on the first-conductivity type semiconductor substrate and sandwiching the pillar structure portion between the isolation insulating portions, wherein the pillar structure portion is formed of a first first-conductivity type pillar layer, a second first-conductivity type pillar layer and a third first-conductivity type pillar layer which sandwich the first first-conductivity type pillar layer, a first second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the second first-conductivity type pillar layer, and a second second-conductivity type pillar layer provided bType: GrantFiled: November 3, 2005Date of Patent: September 9, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Hitoshi Kobayashi, Masanobu Tsuchitani, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Satoshi Taji, Kenichi Tokano
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Patent number: 7391077Abstract: Provided is a semiconductor device including a semiconductor substrate which includes a first semiconductor layer of a first conductivity and a pair of second semiconductor layers disposed on the first semiconductor layer and spaced apart from each other to form a trench therebetween, wherein the second semiconductor layer includes a first impurity-diffused region of the first conductivity extending from a lower surface toward an upper surface of the second semiconductor layer, and a second impurity-diffused region of a second conductivity which extends from the lower surface toward the upper surface and is adjacent to the first impurity-diffused region, an insulating layer covering a sidewall of the trench, and a cap layer which is in contact with the semiconductor substrate and covers an opening of the trench to form an enclosed space in the trench, a material of the cap layer being almost the same as that of the semiconductor substrate.Type: GrantFiled: November 9, 2004Date of Patent: June 24, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Kenichi Tokano, Atsuko Yamashita, Koichi Takahashi, Hideki Okumura, Shingo Sato
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Patent number: 7301202Abstract: A semiconductor substrate of a first conduction type is provided for serving as a common drain to a plurality of power MISFET cells. A middle semiconductor layer is formed on the semiconductor substrate and has a lower impurity concentration than that of the semiconductor substrate. Pillar regions are formed on the middle semiconductor layer and include semiconductor regions of the first conduction type having a lower impurity concentration than that of the middle semiconductor layer.Type: GrantFiled: June 14, 2005Date of Patent: November 27, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Kouzuki, Hideki Okumura, Wataru Saito, Masaru Izumisawa, Masahiko Shiomi, Hitoshi Kobayashi, Kenichi Tokano, Satoshi Yanagisawa, Hironori Yoshioka, Manabu Kimura
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Publication number: 20070148931Abstract: The present invention provides a semiconductor device, which comprises a first semiconductor layer of the first conductivity type having a plurality of trenches formed therein. A second semiconductor layer of the second conductivity type composed of an epitaxial layer is buried in the trenches in the first semiconductor layer. The trench has surface orientations including a surface orientation of a sidewall at an upper stage made slower in epitaxial growth speed than a surface orientation of a sidewall at a lower stage.Type: ApplicationFiled: December 22, 2006Publication date: June 28, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenichi Tokano, Hiroyuki Sugaya
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Publication number: 20060197152Abstract: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.Type: ApplicationFiled: March 1, 2006Publication date: September 7, 2006Applicant: Kabushiki Kaisha ToshibaInventors: Kenichi Tokano, Tetsuo Matsuda, Wataru Saito
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Patent number: 7075149Abstract: A semiconductor device comprises: a semiconductor layer of a first conductivity type; a first semiconductor pillar layer of the first conductivity type; a second semiconductor pillar layer of a second conductivity type; a third semiconductor pillar layer of the first conductivity type; a forth semiconductor pillar layer of the second conductivity type; a fifth semiconductor pillar layer of the first conductivity type provided on the major surface of the semiconductor layer; a first semiconductor base layer of the second conductivity type provided on the second semiconductor pillar layer; a second semiconductor base layer of the second conductivity type provided on the forth semiconductor pillar layer; first semiconductor region of the first conductivity type selectively provided on a surface of the first semiconductor base layer; second semiconductor region of the first conductivity type selectively provided on a surface of the second semiconductor base layer; gate insulating film provided on the first semicoType: GrantFiled: May 13, 2004Date of Patent: July 11, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Shingo Sato, Atsuko Yamashita, Hideki Okumura, Kenichi Tokano
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Publication number: 20060145230Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.Type: ApplicationFiled: December 5, 2005Publication date: July 6, 2006Inventors: Ichiro Omura, Wataru Saito, Tsuneo Ogura, Hiromichi Ohashi, Yoshihiko Saito, Kenichi Tokano
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Publication number: 20060138536Abstract: A semiconductor substrate of a first conduction type is provided for serving as a common drain to a plurality of power MISFET cells. A middle semiconductor layer is formed on the semiconductor substrate and has a lower impurity concentration than that of the semiconductor substrate. Pillar regions are formed on the middle semiconductor layer and include semiconductor regions of the first conduction type having a lower impurity concentration than that of the middle semiconductor layer.Type: ApplicationFiled: June 14, 2005Publication date: June 29, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shigeo Kouzuki, Hideki Okumura, Wataru Saito, Masaru Izumisawa, Masahiko Shiomi, Hitoshi Kobayashi, Kenichi Tokano, Satoshi Yanagisawa, Hironori Yoshioka, Manabu Kimura
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Patent number: 7067870Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.Type: GrantFiled: February 3, 2004Date of Patent: June 27, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Ichiro Omura, Wataru Saito, Tsuneo Ogura, Hiromichi Ohashi, Yoshihiko Saito, Kenichi Tokano
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Publication number: 20060108600Abstract: The present application provides a semiconductor device including a first-conductivity type semiconductor substrate, a pillar structure portion formed on the first-conductivity type semiconductor substrate and formed of five semiconductor pillar layers arranged in one direction parallel to a main surface of the first-conductivity type semiconductor substrate, and isolation insulating portions formed on the first-conductivity type semiconductor substrate and sandwiching the pillar structure portion between the isolation insulating portions, wherein the pillar structure portion is formed of a first first-conductivity type pillar layer, a second first-conductivity type pillar layer and a third first-conductivity type pillar layer which sandwich the first first-conductivity type pillar layer, a first second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the second first-conductivity type pillar layer, and a second second-conductivity type pillar layer provided bType: ApplicationFiled: November 3, 2005Publication date: May 25, 2006Inventors: Hideki Okumura, Hitoshi Kobayashi, Masanobu Tsuchitani, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Satoshi Taji, Kenichi Tokano