Patents by Inventor Kenichi Toyota

Kenichi Toyota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11947305
    Abstract: An apparatus includes a developer container to and from which a replenishment container is attachable and detachable and which includes an accommodating portion and a replenishment port, a transfer portion configured to transfer a developer image on an image bearing member onto a recording material, a supporting tray including a supporting surface configured to support the recording material thereon, and a discharge portion configured to discharge the recording material, onto which the developer image has been transferred, on the supporting surface, wherein the supporting surface has an opening portion opening such that the replenishment port is exposed through the supporting surface, and wherein an opening/closing member configured to be movable between a closed position where the opening/closing member covers the replenishment port and serves as a part of the supporting surface and an open position where the replenishment port is exposed is provided.
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: April 2, 2024
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tomio Noguchi, Masaaki Sato, Kenji Matsuzaka, Koji Fujinaka, Takao Sameshima, Akitoshi Toyota, Yuichiro Inaba, Kenichi Iida
  • Patent number: 5365480
    Abstract: A device is provided for static random access memories (SRAM's), including an apparatus capable of executing more than one kind of logical operation for each memory cell, with a relatively small number of elements, and the same configuration for different types of operations. These operations include (1) the normal read-out/write-in operations; (2) inverting the contents of one sequence of memory cells and storing either the result or the result shifted one bit to the right in a second sequence of memory cells; (3) storing the result of an OR operation between two sequences of memory cells in a third sequence of memory cells; and (4) initializing each memory cell. The left or right node potential of each memory cell may also be individually accessed. Each operation between memory cells is simultaneous with the direct writing of the result into other memory cells, so no temporary holding cells are required and the operation is accomplished at high speed.
    Type: Grant
    Filed: May 27, 1993
    Date of Patent: November 15, 1994
    Assignee: NEC Corporation
    Inventors: Kouichirou Yamamura, Kenichi Toyota, Yoshihiko Kawano