Abstract: A circuit and a method of layout-designing a circuit based on circuit information. The method includes generating layout information including a core region based on the circuit information, laying out an I/O circuit in a region other than the core region on the layout information based on the circuit information, determining a layout-permitted region of pads, which is included in regions other than the core region and a layout region of said I/O circuit, based on circuit information, and laying out the pads in the layout-permitted region.

Abstract: A design support method executed by a computer includes: detecting a layout position of a first terminal in a cell as a first layout position from layout data including a cell of a macro which is arranged at a plurality of orientations, the first terminal being arranged at a first orientation; calculating a second layout position of a first terminal which is arranged at a second orientation which is different from the first orientation based on a variation from the first orientation to the second orientation and the first layout position; associating the second layout position with the first layout position and the layout data; and outputting an association result.

Abstract: The disclosed integrated circuit includes a first and a second power supply wirings, a flip-flop circuit, and a switch element. The first and the second power supply wirings are connected to the common power supplies. The flip-flop circuit is required to hold the stored data even when the voltage supply from the power supplies to the integrated circuit is stopped. The flip-flop circuit is connected to the first power supply wiring. The switch element is a transistor, for example, and switches whether or not the voltage is supplied from the power supplies. The switch element is provided on the second power supply wiring.

Abstract: A method of checking a current density limitation includes checking the current density limitation of a power supply wiring based on an allowable current value, the allowable current value depending on the number of vias connected to the power supply wiring.

Abstract: A design support program stored in a computer readable recording medium and executed by the computer includes computer readable program code stored thereon for causing a computer to execute operations of: selecting a first hierarchy which has different first characteristic information included in wiring layer structure information in a storage device; generating second characteristic information including the first characteristic information; copying wiring layer structure information; and converting the first characteristic information included in the copied wiring layer structure information into the second characteristic information to obtain a converted wiring layer structure information.

Abstract: The disclosed integrated circuit includes a first and a second power supply wirings, a flip-flop circuit, and a switch element. The first and the second power supply wirings are connected to the common power supplies. The flip-flop circuit is required to hold the stored data even when the voltage supply from the power supplies to the integrated circuit is stopped. The flip-flop circuit is connected to the first power supply wiring. The switch element is a transistor, for example, and switches whether or not the voltage is supplied from the power supplies. The switch element is provided on the second power supply wiring.

Abstract: A design support method executed by a computer includes: detecting a layout position of a first terminal in a cell as a first layout position from layout data including a cell of a macro which is arranged at a plurality of orientations, the first terminal being arranged at a first orientation; calculating a second layout position of a first terminal which is arranged at a second orientation which is different from the first orientation based on a variation from the first orientation to the second orientation and the first layout position; associating the second layout position with the first layout position and the layout data; and outputting an association result.

Abstract: A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.

Abstract: A design support program stored in a computer readable recording medium and executed by the computer includes computer readable program code stored thereon for causing a computer to execute operations of: selecting a first hierarchy which has different first characteristic information included in wiring layer structure information in a storage device; generating second characteristic information including the first characteristic information; copying wiring layer structure information; and converting the first characteristic information included in the copied wiring layer structure information into the second characteristic information to obtain a converted wiring layer structure information.

Abstract: In a circuit design method, a computer calculates power of each of cells, calculates an IR drop value by calculating a voltage decreased due to an IR drop for each cell by using the power for each cell, determines whether a difference between a current IR drop value and a previous IR drop is equal to or less than a predetermined value, and defines a voltage after the IR drop occurs for each cell by using the IR drop value when the difference is greater than the predetermined value. The computer repeats calculating the power, calculating the IR drop value, and defining the value after the IR drop occurs until the difference becomes equal to or less than the predetermined value.

Abstract: In a circuit design method, a computer verifies an occurrence of a noise error, specifies a noise allowable value with respect to a cell at which it is determined that the noise error occurs, and determines a parameter value used in a process step. The parameter value satisfies the noise allowable value specified with respect to the cell at which the noise error occurs.

Abstract: A circuit and a method of layout-designing a circuit based on circuit information. The method includes generating layout information including a core region based on the circuit information, laying out an I/O circuit in a region other than the core region on the layout information based on the circuit information, determining a layout-permitted region of pads, which is included in regions other than the core region and a layout region of said I/O circuit, based on circuit information, and laying out the pads in the layout-permitted region.

Abstract: A semiconductor integrated circuit design method includes referring to a best worst coefficient file which stores variation coefficients of capacitance and resistance in each of plural wiring layers under a best condition and a worst condition to form a wiring which is a critical path in a first layer with the smallest variation out of the plural wiring layers, extracting capacitance and resistance corresponding to a wiring layout of the plural wiring layers as a capacitance resistance file, referring to the capacitance resistance file and the best worst coefficient file to generate a best worst capacitance resistance file where capacitance and resistance are defined with taking into consideration the variation on the wiring in each of the plural wiring layers, and performing timing verification of the wiring which is the critical path on the basis of the best worst capacitance resistance file.

Abstract: A designing method of a semiconductor device includes: changing a power supply voltage changing a design data of a semiconductor device with a first power supply voltage into a design data of a semiconductor device with a second power supply voltage which is lower than the first power supply voltage; performing a first static timing analysis detecting the timing error by performing a static timing analysis process based on the delay time of the semiconductor device with the second power supply voltage; and supplying a power supply voltage generating the design data to supply the first power supply voltage to power supply voltage lines of the cell blocks in which cells on paths where the timing errors are detected are included, and to supply the second power supply voltage to the power supply voltage lines of the other cell blocks.

Abstract: Disclosed is a method for designing a semiconductor device so as to prevent the device from being broken even when memory circuits are reset. This method is executed using a computer as follows. First, the computer groups the memory circuits arranged on the basis of arrangement information. Then, the computer inserts a delay circuit between reset lines such that the reset timing of the memory circuits is different in each group. Therefore, the reset timing is different in each group. As a result, a large current flowing during reset is controlled to suppress AC noise so that the semiconductor device can be prevented from being broken.

Abstract: A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.

Abstract: A method of checking a current density limitation includes checking the current density limitation of a power supply wiring based on an allowable current value, the allowable current value depending on the number of vias connected to the power supply wiring.

Abstract: A timing analysis apparatus includes a data extracting unit that extracts objective circuit data concerning an objective circuit to become an objective of a timing analysis from layout data indicating circuits on a large-scale-integration chip; a time calculating unit that calculates a delay time of the objective circuit based on the objective circuit data; a parameter calculating unit that calculates a parameter indicating a size of an arrangement area of the objective circuit based on the objective circuit data; an information calculating unit that calculates variation information concerning a variation of the delay time; and a timing analyzing unit that performs the timing analysis of the objective circuit using the delay time and the variation information.

Abstract: A semiconductor integrated circuit, includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.

Abstract: A circuit design method causing a computer to conduct a circuit design is disclosed, including the step of calculating a power consumption of an entire chip based on a voltage of each of cells after an IR-drop occurs.