Patents by Inventor Ken-ichi Uto

Ken-ichi Uto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6781442
    Abstract: The self-bias adjustment circuit is provided on the previous stage of an internal circuit. This self-bias adjustment circuit adjusts a bias of an input signal and supplies an appropriate signal to the internal circuit. The self-bias adjustment circuit includes a detection circuit 11a that detects the bias voltage of the input signal, and a superposing circuit 11b that superposes a correction voltage for correcting the bias voltage to a predetermined value on the input signal on the basis of the bias voltage detected by the detection circuit. The result signal is supplied to the internal circuit.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: August 24, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Ken-ichi Uto
  • Patent number: 6674328
    Abstract: The amplifier circuit includes differential amplifier circuits (3 to 4); a peak detector circuit (7) for detecting a peak value of an output voltage of a differential amplifier circuit 4 of the last stage; an offset compensation voltage generator circuit (8) for generating an offset compensation voltage for offset compensation on the basis of a detection result of the peak detector circuit (7); and an offset output limiter circuit (9) for limiting the offset compensation voltage generated by the offset compensation voltage generator circuit (8) into a predetermined range and feeding back the limited offset compensation voltage to a differential amplifier circuit (3) of the first stage.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: January 6, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Ken-ichi Uto, Kuniaki Motoshima
  • Publication number: 20020113652
    Abstract: The amplifier circuit includes differential amplifier circuits (3 to 4); a peak detector circuit (7) for detecting a peak value of an output voltage of a differential amplifier circuit 4 of the last stage; an offset compensation voltage generator circuit (8) for generating an offset compensation voltage for offset compensation on the basis of a detection result of the peak detector circuit (7); and an offset output limiter circuit (9) for limiting the offset compensation voltage generated by the offset compensation voltage generator circuit (8) into a predetermined range and feeding back the limited offset compensation voltage to a differential amplifier circuit (3) of the first stage.
    Type: Application
    Filed: February 11, 2002
    Publication date: August 22, 2002
    Inventors: Ken-Ichi Uto, Kuniaki Motoshima
  • Publication number: 20020044009
    Abstract: The self-bias adjustment circuit is provided on the previous stage of an internal circuit. This self-bias adjustment circuit adjusts a bias of an input signal and supplies an appropriate signal to the internal circuit. The self-bias adjustment circuit includes a detection circuit 11a that detects the bias voltage of the input signal, and a superposing circuit 11b that superposes a correction voltage for correcting the bias voltage to a predetermined value on the input signal on the basis of the bias voltage detected by the detection circuit. The result signal is supplied to the internal circuit.
    Type: Application
    Filed: September 7, 2001
    Publication date: April 18, 2002
    Inventor: Ken-ichi Uto