Abstract: A signal processor used to process an analog read signal representing data stored on a magnetic disk allows for a faster read operation without requiring an increase in its circuit area or buffer memory space. The signal processor includes a decision feedback equalizer which selectively provides a feedback signal added to a read signal in reproducing data read from a storage medium. The signal processor also performs error correction. In performing error correction, the load of the error correcting process is detected and the processing speed is altered depending upon the detected load.

Abstract: It is intended to provide a recording-medium operating device, a clock signal generating device for the recoding-medium operating device, and a method for generating a clock signal for the recoding-medium operating device that satisfy both operation with a wide-range data transfer rate using delay line provided with not so large number of stages and high correction accuracy and are advantageous in terms of low power consumption and suppression of noises. A reference clock group Ø0 through Øx different in phase are obtained by a PLL 1. One of the reference clock group is selected by a clock selector 2. A selected clock signal is inputted to a delay circuit 3 and one of output clocks from a delay line 31 is selected by a selector 3. With structure as such, selection by the clock selector 2 and the selector 3 is controlled so as to make phase difference between a clock signal and an RF signal minimum.

Abstract: It is intended to provide a recording-medium operating device, a clock signal generating device for the recoding-medium operating device, and a method for generating a clock signal for the recoding-medium operating device that satisfy both operation with a wide-range data transfer rate using delay line provided with not so large number of stages and high correction accuracy and are advantageous in terms of low power consumption and suppression of noises. A reference clock group Ø0 through Øx different in phase are obtained by a PLL 1. One of the reference clock group is selected by a clock selector 2. A selected clock signal is inputted to a delay circuit 3 and one of output clocks from a delay line 31 is selected by a selector 3. With structure as such, selection by the clock selector 2 and the selector 3 is controlled so as to make phase difference between a clock signal and an RF signal minimum.

Abstract: A signal processor used to process an analog read signal representing data stored on a magnetic disk allows for a faster read operation without requiring an increase in its circuit area or buffer memory space. The signal processor includes a decision feedback equalizer which selectively provides a feedback signal added to a read signal in reproducing data read from a storage medium. The signal processor also performs error correction. In performing error correction, the load of the error correcting process is detected and the processing speed is altered depending upon the detected load.

Abstract: A signal processor used to process an analog read signal representing data stored on a magnetic disk allows for a faster read operation without requiring an increase in its circuit area or buffer memory space. The signal processor includes a decision feedback equalizer which selectively provides a feedback signal added to a read signal in reproducing data read from a storage medium. The signal processor also performs error correction. In performing error correction, the load of the error correcting process is detected and the processing speed is altered depending upon the detected load.

Abstract: A data error correcting method and apparatus reads two dimensional block data having row data and row error correcting codes and column data and column error correcting codes. In the block data, one column error correcting code is assigned to one column data group, and individual column data groups and individual column error correcting codes are alternately arranged. A control unit corrects errors in the block data on a row by row basis using the row error correcting codes and the row data. The control unit also corrects errors on a column by column basis, in parallel with the row errors, using the column error correcting codes and the column data. The control unit includes a compensation input data generator having a data adjustor and a Galois multiplier. The data adjustor computes a Compensation Galois constant for compensating the input order of the data.

Abstract: An error correcting method reducing the time needed to provide error correction using a buffer memory. The method includes performing row error correction by using a plurality of rows of data to produce row-corrected block data and performing column error correction by using the plurality of columns of data to produce column-corrected block data. In addition, at least one of the performing row error correction and performing column error correction operates using a plurality of rows or columns of data in units of a predetermined number of rows or columns so as to provide error correction for the plurality of rows or columns in parallel.