Patents by Inventor Kenichi Yoshizumi

Kenichi Yoshizumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136442
    Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The first insulating layer is provided over the semiconductor layer. The first conductive layer is provided over the first insulating layer. The semiconductor layer includes a first region that overlaps with the first conductive layer and the first insulating layer, a second region that does not overlap with the first conductive layer and overlaps with the first insulating layer, and a third region that overlaps with neither the first conductive layer nor the first insulating layer. The semiconductor layer contains a metal oxide. The second region and the third region contain a first element. The first element is one or more elements selected from boron, phosphorus, aluminum, and magnesium.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 25, 2024
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kenichi OKAZAKI, Masami JINTYOU, Kensuke YOSHIZUMI
  • Publication number: 20240107865
    Abstract: Manufacturing equipment for a light-emitting device with which steps from formation to sealing of a light-emitting element can be successively performed is provided. With the manufacturing equipment for a light-emitting device, a deposition step, a lithography step, and an etching step for forming an organic EL element and a sealing step by formation of a protective layer can be successively performed. Accordingly, a downscaled organic EL element with high luminance and high reliability can be formed. Moreover, the manufacturing equipment can have an in-line system where apparatuses are arranged in the order of process steps for the light-emitting device, resulting in high throughput manufacturing.
    Type: Application
    Filed: January 28, 2022
    Publication date: March 28, 2024
    Inventors: Shingo EGUCHI, Hiroki ADACHI, Kenichi OKAZAKI, Yasumasa YAMANE, Naoto KUSUMOTO, Kensuke YOSHIZUMI, Shunpei YAMAZAKI
  • Patent number: 7755148
    Abstract: Logic LSI includes first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4. The thick-film power switches are formed by thick-film power transistors manufactured in a process common to external input/output circuits I/O. The first power domains include second power domains SPD11 to SPD42 including logic blocks, control circuit blocks SCB1 to SCB4, and thin-film power switches SWN11 to SWN42 that are connected to the thick-film power switches via virtual ground lines VSSM1 to VSSM4, and formed by thin-film power transistors manufactured in a process common to the logic blocks. In this way, power switches having different thickness of gate insulating films from one another are vertically stacked so as to be in a hierarchical structure, and each power switch is individually controlled by a power switch controller and a control circuit block correspondingly to each mode.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: July 13, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yusuke Kanno, Kenichi Yoshizumi
  • Publication number: 20090200617
    Abstract: Logic LSI includes first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4. The thick-film power switches are formed by thick-film power transistors manufactured in a process common to external input/output circuits I/O. The first power domains include second power domains SPD11 to SPD42 including logic blocks, control circuit blocks SCB1 to SCB4, and thin-film power switches SWN11 to SWN42 that are connected to the thick-film power switches via virtual ground lines VSSM1 to VSSM4, and formed by thin-film power transistors manufactured in a process common to the logic blocks. In this way, power switches having different thickness of gate insulating films from one another are vertically stacked so as to be in a hierarchical structure, and each power switch is individually controlled by a power switch controller and a control circuit block correspondingly to each mode.
    Type: Application
    Filed: April 23, 2009
    Publication date: August 13, 2009
    Inventors: Yusuke KANNO, Kenichi Yoshizumi
  • Patent number: 7569899
    Abstract: Logic LSI includes first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4. The thick-film power switches are formed by thick-film power transistors manufactured in a process common to external input/output circuits I/O. The first power domains include second power domains SPD11 to SPD42 including logic blocks, control circuit blocks SCB1 to SCB4, and thin-film power switches SWN11 to SWN42 that are connected to the thick-film power switches via virtual ground lines VSSM1 to VSSM4, and formed by thin-film power transistors manufactured in a process common to the logic blocks. In this way, power switches having different thickness of gate insulating films from one another are vertically stacked so as to be in a hierarchical structure, and each power switch is individually controlled by a power switch controller and a control circuit block correspondingly to each mode.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: August 4, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yusuke Kanno, Kenichi Yoshizumi
  • Publication number: 20090033155
    Abstract: A semiconductor integrated circuit includes a first power source wiring line (VDD1) for conveying a first supply voltage; a logic circuit block (CKB) which is operable by being fed with the first supply voltage; a second power source wiring line (VDD2) for propagating a second supply voltage which is higher in level than the first supply voltage; a switch (MPS) which is capable of connecting the first power source wiring line and the second power source wiring line; and a control circuit (VCTLC) which can control the switch when the first supply voltage has undergone a potential drop, so as to intermittently connect the second power source wiring line to the first power source wiring line. Owing to the control of the control circuit, a local supply voltage fluctuation is prevented, thereby to achieve the enhancement of the power source performance of the semiconductor integrated circuit.
    Type: Application
    Filed: May 22, 2008
    Publication date: February 5, 2009
    Inventors: Yusuke KANNO, Kenichi Yoshizumi
  • Publication number: 20080054946
    Abstract: Logic LSI includes first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4. The thick-film power switches are formed by thick-film power transistors manufactured in a process common to external input/output circuits I/O. The first power domains include second power domains SPD11 to SPD42 including logic blocks, control circuit blocks SCB1 to SCB4, and thin-film power switches SWN11 to SWN42 that are connected to the thick-film power switches via virtual ground lines VSSM1 to VSSM4, and formed by thin-film power transistors manufactured in a process common to the logic blocks. In this way, power switches having different thickness of gate insulating films from one another are vertically stacked so as to be in a hierarchical structure, and each power switch is individually controlled by a power switch controller and a control circuit block correspondingly to each mode.
    Type: Application
    Filed: July 12, 2007
    Publication date: March 6, 2008
    Inventors: Yusuke KANNO, Kenichi Yoshizumi