Patents by Inventor Kenichiro Chomei
Kenichiro Chomei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10923444Abstract: A semiconductor chip (2,3) is mounted on a heat sink (1). Plural lead terminals (5,6) are connected to the semiconductor chip (2,3). The plural lead terminals (5,6) include a first lead terminal through which a high frequency signal passes. Plural dielectric materials (10,11) separated from each other are individually provided between the plural lead terminals (5,6) and the heat sink (1). Sealing resin (12) seals the semiconductor chip (2,3), the plural lead terminals (5,6) and the plural dielectric materials (10,11).Type: GrantFiled: May 26, 2017Date of Patent: February 16, 2021Assignee: Mitsubishi Electric CorporationInventors: Katsumi Miyawaki, Kenichiro Chomei
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Patent number: 9800210Abstract: A power amplifier includes: a plurality of FET cells connected in parallel to each other; a plurality of first resistors connected between gate terminals of the plurality of FET cells and grounding terminals respectively; a plurality of second resistors having one ends connected to the gate terminals of the plurality of FET cells respectively and other ends connected to each other; a plurality of capacitors connected in parallel to the plurality of second resistors respectively; and a third resistor connected between a connection point of the other ends of the plurality of second resistors and a power supply terminal, wherein the first resistors have temperature coefficients of resistance greater than those of the second and third resistors and are arranged closer to the corresponding FET cells than the third resistor.Type: GrantFiled: August 29, 2016Date of Patent: October 24, 2017Assignee: Mitsubishi Electric CorporationInventors: Katsuya Kato, Naoki Kosaka, Eri Fukuda, Shigeru Fujiwara, Atsushi Okamura, Kenichiro Chomei
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Publication number: 20170207753Abstract: A power amplifier includes: a plurality of FET cells connected in parallel to each other; a plurality of first resistors connected between gate terminals of the plurality of FET cells and grounding terminals respectively; a plurality of second resistors having one ends connected to the gate terminals of the plurality of FET cells respectively and other ends connected to each other; a plurality of capacitors connected in parallel to the plurality of second resistors respectively; and a third resistor connected between a connection point of the other ends of the plurality of second resistors and a power supply terminal, wherein the first resistors have temperature coefficients of resistance greater than those of the second and third resistors and are arranged closer to the corresponding FET cells than the third resistor.Type: ApplicationFiled: August 29, 2016Publication date: July 20, 2017Applicant: Mitsubishi Electric CorporationInventors: Katsuya KATO, Naoki KOSAKA, Eri FUKUDA, Shigeru FUJIWARA, Atsushi OKAMURA, Kenichiro CHOMEI
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Patent number: 9627300Abstract: An amplifier includes a package, a transistor chip having a gate pad and a drain pad formed elongately, the transistor chip being provided in the package, and a plurality of drain bonding wires connected to the drain pad, wherein the plurality of drain bonding wires include a first outer-most bonding wire connected to one of two end portions of the drain pad, a second outer-most bonding wire connected to the other of the two end portions of the drain pad, and an intermediate bonding wire interposed between the first outer-most bonding wire and the second outer-most bonding wire, each of the plurality of drain bonding wires is longer than 1 mm, and the first outer-most bonding wire and the second outer-most bonding wire have loop heights larger than a loop height that the intermediate bonding wire has.Type: GrantFiled: May 17, 2016Date of Patent: April 18, 2017Assignee: Mitsubishi Electric CorporationInventors: Naoki Kosaka, Shohei Imai, Atsushi Okamura, Shinichi Miwa, Kenichiro Chomei, Yoshinobu Sasaki, Kenichi Horiguchi
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Publication number: 20170077012Abstract: An amplifier includes a package, a transistor chip having a gate pad and a drain pad formed elongately, the transistor chip being provided in the package, and a plurality of drain bonding wires connected to the drain pad, wherein the plurality of drain bonding wires include a first outer-most bonding wire connected to one of two end portions of the drain pad, a second outer-most bonding wire connected to the other of the two end portions of the drain pad, and an intermediate bonding wire interposed between the first outer-most bonding wire and the second outer-most bonding wire, each of the plurality of drain bonding wires is longer than 1 mm, and the first outer-most bonding wire and the second outer-most bonding wire have loop heights larger than a loop height that the intermediate bonding wire has.Type: ApplicationFiled: May 17, 2016Publication date: March 16, 2017Applicant: Mitsubishi Electric CorporationInventors: Naoki KOSAKA, Shohei IMAI, Atsushi OKAMURA, Shinichi MIWA, Kenichiro CHOMEI, Yoshinobu SASAKI, Kenichi HORIGUCHI
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Patent number: 7365415Abstract: A semiconductor device has a mounting substrate and a semiconductor package mounted on the mounting substrate. The mounting substrate has a substrate body, input/output line conductors on the upper surface of the substrate body, a front-face grounding conductor on the upper surface of the substrate body, spaced from the input/output line conductors, and a lower surface grounding conductor formed on the lower surface of the substrate body and electrically connected to the front-face grounding conductor. The semiconductor package has input/output terminals electrically connected to end portions of the input/output line conductors, a grounding terminal electrically connected to the front-face grounding conductor, and a semiconductor element die-bonded on the grounding terminal and electrically connected to the input/output terminals.Type: GrantFiled: October 10, 2006Date of Patent: April 29, 2008Assignee: Mitsubishi Electric CorporationInventor: Kenichiro Chomei
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Patent number: 7323763Abstract: A semiconductor device having an improved voltage control oscillator circuit is provided. The voltage control oscillator circuit includes, in combination, a variable-capacitance element and at least one bipolar transistor on a single semiconductor substrate. The variable-capacitance element includes reversely serially connected PN junctions, and junctions are formed by a single common collector layer and separated base layers on the common collector layer. The capacitance of the variable-capacitance element is generated between respective base layers of the PN junctions with the common collector layer, and varies in correspondence with the voltage applied to the common collector layer.Type: GrantFiled: July 7, 2005Date of Patent: January 29, 2008Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Satoshi Suzuki, Takayuki Matsuzuka, Kenichiro Chomei
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Publication number: 20070290334Abstract: A semiconductor device has a mounting substrate and a semiconductor package mounted on the mounting substrate. The mounting substrate has a substrate body, input/output line conductors on the upper surface of the substrate body, a front-face grounding conductor on the upper surface of the substrate body, spaced from the input/output line conductors, and a lower surface grounding conductor formed on the lower surface of the substrate body and electrically connected to the front-face grounding conductor. The semiconductor package has input/output terminals electrically connected to end portions of the input/output line conductors, a grounding terminal electrically connected to the front-face grounding conductor, and a semiconductor element die-bonded on the grounding terminal and electrically connected to the input/output terminals.Type: ApplicationFiled: October 10, 2006Publication date: December 20, 2007Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Kenichiro Chomei
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Publication number: 20060006418Abstract: A semiconductor device having an improved voltage control oscillator circuit is provided. The voltage control oscillator circuit includes, in combination, a variable-capacitance element and at least one bipolar transistor on a single semiconductor substrate. The variable-capacitance element includes reversely serially connected PN junctions, and junctions are formed by a single common collector layer and separated base layers on the common collector layer. The capacitance of the variable-capacitance element is generated between respective base layers of the PN junctions with the common collector layer, and varies in correspondence with the voltage applied to the common collector layer.Type: ApplicationFiled: July 7, 2005Publication date: January 12, 2006Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Satoshi Suzuki, Takayuki Matsuzuka, Kenichiro Chomei