Patents by Inventor Kenichiro Furuta

Kenichiro Furuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11567830
    Abstract: A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to read a received word from the non-volatile memory, estimate noise by using a plurality of different models for estimating the noise included in the received word to obtain a plurality of noise estimation values, select one noise estimation value from the plurality of noise estimation values, update the received word by using a value obtained by subtracting the selected noise estimation value from the read received word, and decode the updated received word by using a belief-propagation method.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: January 31, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Yuma Yoshinaga, Tomoya Kodama, Osamu Torii, Kenichiro Furuta, Ryota Yoshizawa
  • Patent number: 11418219
    Abstract: According to one embodiment, a learning device includes a noise generation unit, a decoding unit, a generation unit, and a learning unit. The noise generation unit outputs a second code word which corresponds to a first code word to which noise has been added. The decoding unit decodes the second code word and outputs a third code word. The generation unit generates learning data for learning a weight in message passing decoding in which the weight and a message to be transmitted are multiplied, based on whether or not decoding of the second code word into the third code word has been successful. The learning unit determines a value for the weight in the message passing decoding by using the learning data.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: August 16, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Ryota Yoshizawa, Kenichiro Furuta, Yuma Yoshinaga, Osamu Torii, Tomoya Kodama
  • Publication number: 20210295153
    Abstract: A learning device includes an encoding unit, a plurality of permutation units, a plurality of decoding units, a selection unit, and a learning unit. The encoding unit is configured generate an encoded word by encoding a transmission word. The permutation units are configured to permutate the encoded word according to different permutation manners to generate a plurality of permutated encoded words. The decoding units are configured to perform message passing decoding on the plurality of permutated encoded words, to generate a plurality of decoded words. The message passing decoding involves weighting of values of a word transmitted during the message passing decoding. The selection unit is configured to select one or more of the decoded words. The learning unit is configured to perform learning of weighting values of the weighting based on the transmission word and the selected one or more of the decoded words.
    Type: Application
    Filed: February 24, 2021
    Publication date: September 23, 2021
    Inventors: Ryota YOSHIZAWA, Kenichiro FURUTA, Yuma YOSHINAGA, Osamu TORII, Tomoya KODAMA
  • Publication number: 20210279133
    Abstract: A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to read a received word from the non-volatile memory, estimate noise by using a plurality of different models for estimating the noise included in the received word to obtain a plurality of noise estimation values, select one noise estimation value from the plurality of noise estimation values, update the received word by using a value obtained by subtracting the selected noise estimation value from the read received word, and decode the updated received word by using a belief-propagation method.
    Type: Application
    Filed: February 24, 2021
    Publication date: September 9, 2021
    Applicant: Kioxia Corporation
    Inventors: Yuma YOSHINAGA, Tomoya KODAMA, Osamu TORII, Kenichiro FURUTA, Ryota YOSHIZAWA
  • Publication number: 20210242888
    Abstract: According to one embodiment, a learning device includes a noise generation unit, a decoding unit, a generation unit, and a learning unit. The noise generation unit outputs a second code word which corresponds to a first code word to which noise has been added. The decoding unit decodes the second code word and outputs a third code word. The generation unit generates learning data for learning a weight in message passing decoding in which the weight and a message to be transmitted are multiplied, based on whether or not decoding of the second code word into the third code word has been successful. The learning unit determines a value for the weight in the message passing decoding by using the learning data.
    Type: Application
    Filed: August 27, 2020
    Publication date: August 5, 2021
    Inventors: Ryota YOSHIZAWA, Kenichiro FURUTA, Yuma YOSHINAGA, Osamu TORII, Tomoya KODAMA
  • Patent number: 10822471
    Abstract: A friction drive belt (B) includes a belt body (10) that is wrapped around pulleys in contact therewith to transmit power. At least a pulley contact portion (15) of the belt main body (10) is made of a rubber composition containing 30-80 parts by mass of at least one layered silicate selected from a smectite group and a vermiculite group, per 100 parts by mass of raw rubber containing an ethylene-?-olefin elastomer.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: November 3, 2020
    Assignee: BANDO CHEMICAL INDUSTRIES, LTD.
    Inventors: Shinji Takahashi, Kenichiro Furuta, Hiroyuki Shiriike, Tomoyuki Yamada, Hiroyuki Tachibana
  • Patent number: 9134708
    Abstract: An example information processing device includes first and second receiving units, a deciding unit, and first and second transmitting units. The first receiving unit receives adjustment limit information from a plurality of first external devices. The deciding unit determines adjustment rules on the basis of the adjustment limit information. The first transmitting unit transmits the adjustment rules to second and third external devices. The second receiving unit receives determination information from a fourth external device. The second transmitting unit transmits the adjustment rules to the first external devices when integrated schedule information satisfies a condition. When the integrated schedule information does not satisfy the condition, the deciding unit changes the adjustment rules. When the deciding unit has changed the adjustment rules, the first transmitting unit transmits new adjustment rules to the second and third external devices.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: September 15, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Furuta, Yuichi Komano, Shinji Yamanaka, Satoshi Ito, Hideyuki Aisu, Tomoshi Otsuki, Masatake Sakuma, Taichi Isogai
  • Patent number: 8924448
    Abstract: An arithmetic device includes an input unit inputting data that are elements of a group; a converting unit is configured, when the input data are in a second representation, to convert the input data into a first representation and to perform arithmetic operation on the converted first representation using an operand in the first representation in which at least one subcomponent is a zero element to convert the converted first representation into first converted data expressed in the first representation, and when the input data are in the first representation, to perform arithmetic operation on the input data using the operand in the first representation in which at least one subcomponent is a zero element to convert the input data into second converted data expressed in the first representation; and an operating unit that performs arithmetic processing on the first or the second converted data using secret information.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: December 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taichi Isogai, Kenichiro Furuta, Hirofumi Muratani, Kenji Ohkuma, Tomoko Yonemura, Yoshikazu Hanatani, Atsushi Shimbo, Hanae Ikeda, Yuichi Komano
  • Patent number: 8782114
    Abstract: According to one embodiment, a representation converting unit converts a set of n elements (h0, h1, . . . , hn?1) (hi: a member of a finite field Fp^m, 0?i?n?1) that is a projective representation of a member g of an n-th degree algebraic torus Tn(Fp^m) (n: positive integer, p: prime number, m: positive integer) into a limited projected representation expressed by a set of n elements (h?0, h?1, . . . , h?n?1) (h?i: a member of the finite field Fp^m, 0?i?n?1) in which at least one element out of the n elements is a zero element 0 or an identity element 1. An arithmetic unit omits part of Fp^m operation that is arithmetic operation in the finite field Fp^m based on a fact that an element in the set of n elements (h?0, h?1, . . . , h?n?1) represented by the limited projective representation is a zero element “0” or an identity element “1” when performing Fp^mn operation that is arithmetic operation of a finite field Fp^mn in combination with the Fp^m operation.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Yonemura, Taichi Isogai, Hirofumi Muratani, Atsushi Shimbo, Yoshikazu Hanatani, Kenichiro Furuta, Kenji Ohkuma, Yuichi Komano, Hanae Ikeda
  • Patent number: 8776253
    Abstract: According to an embodiment, an authority changing device includes a first determiner, a second determiner, and a changing unit. A first authority is defined by a first combination of first to third item values, and a second authority is defined by a second combination of the fourth to sixth item values. The first determiner uses a logical expression to determine whether the change from the first authority to the second authority is possible, not possible, or unknown. The second determiner uses a first table to determine the availability of change from the first authority to the second authority when the availability of the change is determined to be unknown. The changing unit changes the first authority to the second authority when the change is determined to be possible.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Furuta, Satoshi Ito, Haruhiko Toyama, Hiroshi Isozaki, Toshiaki Asano
  • Patent number: 8675874
    Abstract: A compressing unit compresses an element on an algebraic torus into affine representation according to a compression map. A determining unit determines whether a target element on the algebraic torus to be compressed is an exceptional point representing an element on the algebraic torus that cannot be compressed by the compression map. The compressing unit generates, when it is determined that the target element is the exceptional point, a processing result including exceptional information indicating that the target element is the exceptional point, and generates, when it is determined that the target element is not the exceptional point, a processing result including affine representation obtained by compressing the target element according to the compression map.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: March 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirofumi Muratani, Tomoko Yonemura, Atsushi Shimbo, Kenji Ohkuma, Taichi Isogai, Yuichi Komano, Kenichiro Furuta, Yoshikazu Hanatani
  • Patent number: 8543630
    Abstract: In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a plurality of elements. The computing device performs a multiplication operation on a base field using the accepted elements, and obtains a multiplication value. The multiplication operation is determined by a condition under which the element in the finite field is placed in an algebraic torus. The computing device performs an addition and subtraction operation using the obtained multiplication value and the accepted elements, and obtains a calculation result of the square of the element. The addition and subtraction operation is determined by the condition. The computing device then outputs the calculation result.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: September 24, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Yonemura, Hirofumi Muratani, Atsushi Shimbo, Kenji Ohkuma, Taichi Isogai, Yuichi Komano, Kenichiro Furuta, Yoshikazu Hanatani
  • Publication number: 20130247211
    Abstract: According to an embodiment, an authority changing device includes a first determiner, a second determiner, and a changing unit. A first authority is defined by a first combination of first to third item values, and a second authority is defined by a second combination of the fourth to sixth item values. The first determiner uses a logical expression to determine whether the change from the first authority to the second authority is possible, not possible, or unknown. The second determiner uses a first table to determine the availability of change from the first authority to the second authority when the availability of the change is determined to be unknown. The changing unit changes the first authority to the second authority when the change is determined to be possible.
    Type: Application
    Filed: December 28, 2012
    Publication date: September 19, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenichiro FURUTA, Satoshi ITO, Haruhiko TOYAMA, Hiroshi ISOZAKI, Toshiaki ASANO
  • Patent number: 8533243
    Abstract: When converting an affine representation representing a 2r-th degree algebraic torus T2r(Fq) (r is a prime number, and q is an integer) to a projective representation representing a quadratic algebraic torus T2(Fq^r), a representation converting apparatus acquires member (c0, c1, . . . , cr-2), (ci is a member of a finite field Fq, where 0?i?r?2) of a 2r-th degree algebraic torus T2r(Fq) represented by the affine representation. The apparatus performs a multiplication operation on the acquired member. The multiplication operation is determined by a condition under which a member of a quadratic algebraic torus T2(Fq^r) is included in the 2r-th degree algebraic torus T2r(Fq), a modulus and a base of a quadratic extension, and a modulus and a base of an r-th degree extension. The representation converting apparatus then performs an addition and subtraction operation determined by the condition, the moduli, and the bases.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: September 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Yonemura, Hirofumi Muratani, Kenji Ohkuma, Hanae Ikeda, Taichi Isogai, Kenichiro Furuta, Yoshikazu Hanatani
  • Publication number: 20130166080
    Abstract: An example information processing device includes first and second receiving units, a deciding unit, and first and second transmitting units. The first receiving unit receives adjustment limit information from a plurality of first external devices. The deciding unit determines adjustment rules on the basis of the adjustment limit information. The first transmitting unit transmits the adjustment rules to second and third external devices. The second receiving unit receives determination information from a fourth external device. The second transmitting unit transmits the adjustment rules to the first external devices when integrated schedule information satisfies a condition. When the integrated schedule information does not satisfy the condition, the deciding unit changes the adjustment rules. When the deciding unit has changed the adjustment rules, the first transmitting unit transmits new adjustment rules to the second and third external devices.
    Type: Application
    Filed: December 27, 2012
    Publication date: June 27, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenichiro Furuta, Yuichi Komano, Shinji Yamanaka, Satoshi Ito, Hideyuki Aisu, Tomoshi Otsuki, Masatake Sakuma, Taichi Isogai
  • Patent number: 8438205
    Abstract: In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a plurality of elements. The computing device performs a multiplication operation on a base field using the accepted elements, and obtains a multiplication value. The multiplication operation is determined by a condition under which the element in the finite field is placed in an algebraic torus. The computing device performs an addition and subtraction operation using the obtained multiplication value and the accepted elements, and obtains a calculation result of the square of the element. The addition and subtraction operation is determined by the condition. The computing device then outputs the calculation result.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: May 7, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Yonemura, Hirofumi Muratani, Atsushi Shimbo, Kenji Ohkuma, Taichi Isogai, Yuichi Komano, Kenichiro Furuta, Yoshikazu Hanatani
  • Publication number: 20120239721
    Abstract: An arithmetic device includes an input unit inputting data that are elements of a group; a converting unit is configured, when the input data are in a second representation, to convert the input data into a first representation and to perform arithmetic operation on the converted first representation using an operand in the first representation in which at least one subcomponent is a zero element to convert the converted first representation into first converted data expressed in the first representation, and when the input data are in the first representation, to perform arithmetic operation on the input data using the operand in the first representation in which at least one subcomponent is a zero element to convert the input data into second converted data expressed in the first representation; and an operating unit that performs arithmetic processing on the first or the second converted data using secret information.
    Type: Application
    Filed: March 16, 2012
    Publication date: September 20, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Taichi ISOGAI, Kenichiro Furuta, Hirofumi Muratani, Kenji Ohkuma, Tomoko Yonemura, Yoshikazu Hanatani, Atsushi Shimbo, Hanae Ikeda, Yuichi Komano
  • Patent number: 8233616
    Abstract: An encryption processing unit executes an arithmetic operation decided in advance and outputs an arithmetic result as an element on an algebraic torus. A compressing unit outputs, when the arithmetic result is an exceptional point representing an element on the algebraic torus that cannot be compressed by a compression map for compressing an element on the algebraic torus into affine representation, a compression result obtained by compressing the arithmetic result according to the compression map and outputs, when the arithmetic result is the exceptional point, an element belonging to a specific set decided in advance that does not overlap a set to which a compression result obtained by compressing the arithmetic result, which is not the exceptional point, belongs.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: July 31, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirofumi Muratani, Tomoko Yonemura, Atsushi Shimbo, Kenji Ohkuma, Taichi Isogai, Yuichi Komano, Kenichiro Furuta, Yoshikazu Hanatani, Hanae Ikeda
  • Publication number: 20120124114
    Abstract: According to one embodiment, a representation converting unit converts a set of n elements (h0, h1, . . . , hn?1) (hi: a member of a finite field Fp?m, 0?i?n?1) that is a projective representation of a member g of an n-th degree algebraic torus Tn(Fp?m) (n: positive integer, p: prime number, m: positive integer) into a limited projected representation expressed by a set of n elements (h?0, h?1, . . . , h?n?1) (h?i: a member of the finite field Fp?m, 0?i?n?1) in which at least one element out of the n elements is a zero element 0 or an identity element 1. An arithmetic unit omits part of Fp?m operation that is arithmetic operation in the finite field Fp?m based on a fact that an element in the set of n elements (h?0, h?1, . . . , h?n?1) represented by the limited projective representation is a zero element “0” or an identity element “1” when performing Fp?mn operation that is arithmetic operation of a finite field Fp?mn in combination with the Fp?m operation.
    Type: Application
    Filed: January 23, 2012
    Publication date: May 17, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko YONEMURA, Taichi ISOGAI, Hirofumi MURATANI, Atsushi SHIMBO, Yoshikazu HANATANI, Kenichiro FURUTA, Kenji OHKUMA, Yuichi KOMANO, Hanae IKEDA
  • Publication number: 20110300981
    Abstract: A friction drive belt (B) includes a belt body (10) that is wrapped around pulleys in contact therewith to transmit power. At least a pulley contact portion (15) of the belt main body (10) is made of a rubber composition containing 30-80 parts by mass of at least one layered silicate selected from a smectite group and a vermiculite group, per 100 parts by mass of raw rubber containing an ethylene-?-olefin elastomer.
    Type: Application
    Filed: February 24, 2010
    Publication date: December 8, 2011
    Applicant: BANDO CHEMICAL INDUSTRIES, LTD
    Inventors: Shinji Takahashi, Kenichiro Furuta, Hiroyuki Shiriike, Tomoyuki Yamada, Hiroyuki Tachibana