Patents by Inventor Kenichiro KURAHASHI
Kenichiro KURAHASHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11107685Abstract: The semiconductor manufacturing device includes: a lower substrate support base configured to support a diamond substrate; an upper substrate support base configured to support a semiconductor substrate; a support base drive unit configured to move the lower substrate support base and the upper substrate support base to bring the diamond substrate and the semiconductor substrate into close contact with each other under a state in which a pressure is applied to the diamond substrate and the semiconductor substrate in a thickness direction; and a second mechanism configured to deform a surface of the upper substrate support base opposed to the lower substrate support base so that a surface of the semiconductor substrate opposed to the diamond substrate forms a parallel surface or a parallel plane with respect to a surface of the diamond substrate opposed to the semiconductor substrate.Type: GrantFiled: February 1, 2018Date of Patent: August 31, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Keisuke Nakamura, Muneyoshi Suita, Akifumi Imai, Kenichiro Kurahashi, Tomohiro Shinagawa, Takashi Matsuda, Koji Yoshitsugu, Eiji Yagyu, Kunihiko Nishimura
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Publication number: 20190362974Abstract: The semiconductor manufacturing device includes: a lower substrate support base configured to support a diamond substrate; an upper substrate support base configured to support a semiconductor substrate; a support base drive unit configured to move the lower substrate support base and the upper substrate support base to bring the diamond substrate and the semiconductor substrate into close contact with each other under a state in which a pressure is applied to the diamond substrate and the semiconductor substrate in a thickness direction; and a second mechanism configured to deform a surface of the upper substrate support base opposed to the lower substrate support base so that a surface of the semiconductor substrate opposed to the diamond substrate forms a parallel surface or a parallel plane with respect to a surface of the diamond substrate opposed to the semiconductor substrate.Type: ApplicationFiled: February 1, 2018Publication date: November 28, 2019Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Keisuke NAKAMURA, Muneyoshi SUITA, Akifumi IMAI, Kenichiro KURAHASHI, Tomohiro SHINAGAWA, Takashi MATSUDA, Koji YOSHITSUGU, Eiji YAGYU, Kunihiko NISHIMURA
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Patent number: 9893210Abstract: A semiconductor device includes: a substrate; a nitride semiconductor layer on the substrate; a source electrode, a drain electrode and a gate electrode on the nitride semiconductor layer; and a SiN surface protective film covering the nitride semiconductor layer, wherein a composition ratio Si/N of Si and N that form a Si—N bond of the SiN surface protective film is 0.751 to 0.801.Type: GrantFiled: June 6, 2016Date of Patent: February 13, 2018Assignee: Mitsubishi Electric CorporationInventors: Kenichiro Kurahashi, Takuma Nanjo, Muneyoshi Suita, Akifumi Imai, Eiji Yagyu, Hiroyuki Okazaki
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Patent number: 9640647Abstract: A semiconductor device includes: a substrate; a nitride semiconductor film on the substrate; a schottky electrode on the nitride semiconductor film; a first insulating film on the nitride semiconductor film, contacting at least part of a side surface of the schottky electrode, forming an interface with the nitride semiconductor film and formed of SiN; and a second insulating film covering the schottky electrode and the first insulating film and formed of AlO whose atomic layers are alternately disposed.Type: GrantFiled: May 3, 2016Date of Patent: May 2, 2017Assignee: Mitsubishi Electric CorporationInventors: Hiroyuki Okazaki, Kenichiro Kurahashi, Hidetoshi Koyama, Toshiaki Kitano, Yoshitaka Kamo
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Publication number: 20170092783Abstract: A semiconductor device includes: a substrate; a nitride semiconductor layer on the substrate; a source electrode, a drain electrode and a gate electrode on the nitride semiconductor layer; and a SiN surface protective film covering the nitride semiconductor layer, wherein a composition ratio Si/N of Si and N that form a Si—N bond of the SiN surface protective film is 0.751 to 0.Type: ApplicationFiled: June 6, 2016Publication date: March 30, 2017Applicant: Mitsubishi Electric CorporationInventors: Kenichiro KURAHASHI, Takuma NANJO, Muneyoshi SUITA, Akifumi IMAI, Eiji YAGYU, Hiroyuki OKAZAKI
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Publication number: 20170077275Abstract: A semiconductor device includes: a substrate; a nitride semiconductor film on the substrate; a schottky electrode on the nitride semiconductor film; a first insulating film on the nitride semiconductor film, contacting at least part of a side surface of the schottky electrode, forming an interface with the nitride semiconductor film and formed of SiN; and a second insulating film covering the schottky electrode and the first insulating film and formed of AlO whose atomic layers are alternately disposed.Type: ApplicationFiled: May 3, 2016Publication date: March 16, 2017Applicant: Mitsubishi Electric CorporationInventors: Hiroyuki OKAZAKI, Kenichiro KURAHASHI, Hidetoshi KOYAMA, Toshiaki KITANO, Yoshitaka KAMO
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Publication number: 20150228756Abstract: A semiconductor device includes an Alx1Ga1-x1N (0?x1?1) barrier layer, and a gate electrode that is disposed on a surface of the Alx1Ga1-x1N (0?x1?1) barrier layer, forms a Schottky junction with the surface of the Alx1Ga1-x1N (0?x1?1) barrier layer, and has an Ni single-layer structure. Annealing processing is performed with respect to the gate electrode at a temperature of 500° C. or above under a nitrogen atmosphere to form a reaction layer between the surface of the Alx1Ga1-x1N (0?x1?1) barrier layer and the gate electrode.Type: ApplicationFiled: February 2, 2015Publication date: August 13, 2015Applicant: Mitsubishi Electric CorporationInventors: Kenichiro KURAHASHI, Takuma Nanjo, Muneyoshi Suita, Yosuke Suzuki, Akifumi Imai, Marika Nakamura, Eiji Yagyu
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Publication number: 20150069408Abstract: A laminate includes a surface on which a gate electrode is provided, and is made of a nitride semiconductor. The laminate includes a first layer having a first band gap, and a second layer provided between the first layer and the surface and having a second band gap which is larger than the first band gap. The first and second layers and form a joint surface by a hetero junction. The surface includes a surface defect density equal to or smaller than 1.7×106 cm?2.Type: ApplicationFiled: August 28, 2014Publication date: March 12, 2015Applicant: Mitsubishi Electric CorporationInventors: Takuma NANJO, Akifumi IMAI, Yosuke SUZUKI, Muneyoshi SUITA, Kenichiro KURAHASHI, Marika NAKAMURA, Eiji YAGYU
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Patent number: 8912099Abstract: A method of manufacturing a semiconductor device includes forming a first layer on a semiconductor layer, forming a second layer on the first layer, forming a patterned mask on the second layer, etching and removing a portion of the second layer that is not covered by the patterned mask, wet etching the first layer to a width which is less than the width of the patterned mask, after the wet etching, forming an insulating layer on the semiconductor layer, removing the first layer and the second layer to form an opening in the insulating layer, and forming a gate electrode on a surface of the semiconductor layer exposed through the opening.Type: GrantFiled: July 30, 2013Date of Patent: December 16, 2014Assignee: Mitsubishi Electric CorporationInventors: Kenichiro Kurahashi, Yoshitaka Kamo, Yoshitsugu Yamamoto
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Publication number: 20140134835Abstract: A method of manufacturing a semiconductor device includes forming a first layer on a semiconductor layer, forming a second layer on the first layer, forming a patterned mask on the second layer, etching and removing a portion of the second layer that is not covered by the patterned mask, wet etching the first layer to a width which is less than the width of the patterned mask, after the wet etching, forming an insulating layer on the semiconductor layer, removing the first layer and the second layer to form an opening in the insulating layer, and forming a gate electrode on a surface of the semiconductor layer exposed through the opening.Type: ApplicationFiled: July 30, 2013Publication date: May 15, 2014Applicant: Mitsubishi Electric CorporationInventors: Kenichiro Kurahashi, Yoshitaka Kamo, Yoshitsugu Yamamoto
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Patent number: 8524601Abstract: A method of manufacturing a semiconductor device includes forming an insulating film on a surface of a semiconductor layer, forming a resist on a surface of the insulating film, the resist having an opening, forming a hardened layer on an inner circumference of the resist by attaching a pattern shrinking agent to the resist, the pattern shrinking agent undergoing a cross-linking reaction with the resist, etching the insulating film using the resist and the hardened layer as masks, removing the hardened layer, and forming a metal layer on a surface of the semiconductor layer, on a surface of the insulating film, and on a surface of the resist. The method further includes removing the resist and the portion of the metal layer on the surface of the resist by lift-off.Type: GrantFiled: December 22, 2011Date of Patent: September 3, 2013Assignee: Mitsubishi Electric CorporationInventors: Kenichiro Kurahashi, Hidetoshi Koyama, Kazuyuki Onoe
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Publication number: 20120208365Abstract: A method of manufacturing a semiconductor device includes forming an insulating film on a surface of a semiconductor layer, forming a resist on a surface of the insulating film, the resist having an opening, forming a hardened layer on an inner circumference of the resist by attaching a pattern shrinking agent to the resist, the pattern shrinking agent undergoing a cross-linking reaction with the resist, etching the insulating film using the resist and the hardened layer as masks, removing the hardened layer, and forming a metal layer on a surface of the semiconductor layer, on a surface of the insulating film, and on a surface of the resist. The method further includes removing the resist and the portion of the metal layer on the surface of the resist by lift-off.Type: ApplicationFiled: December 22, 2011Publication date: August 16, 2012Applicant: Mitsubishi Electric CorporationInventors: Kenichiro KURAHASHI, Hidetoshi Koyama, Kazuyuki Onoe