Abstract: A machine tool system is equipped with a machine tool and a controller. The machine tool is equipped with a machine tool body and at least one temperature sensor that acquires temperature data of the machine tool body. The controller is equipped with a storage that stores the temperature data acquired in time-series by the temperature sensor, and an auxiliary power supply that supplies power to the temperature sensor and the storage when the supply of power to the machine tool body is stopped. The controller controls the machine tool by using the temperature data over a predetermined time range stored in the storage, and selects, in response to a charge state of the auxiliary power supply, the temperature data to be used in first control after the supply of power to the machine tool body is resumed.

Abstract: The memory error determination device includes a processor configured to: detect a memory element in which an error has occurred in each of a plurality of layers included in a memory being three-dimensionally stacked, specify a position of each memory element in which the error has occurred in each of the plurality of layers, and determine that, when the position of each memory element in which the error has occurred is linearly aligned across a predetermined number of layers among the plurality of layers, the predetermined number being two or more, an error that has occurred in the memory is a soft error due to radiation incident on the memory.

Abstract: The program generation apparatus includes a terminal detection unit for detecting position information including a position of a first terminal of an input/output apparatus to which an electrical wiring is connected. A display control unit displays, on a display part, a control program and position information of the first terminal detected by the terminal detection unit. The operation detection unit detects a symbol indicating the device specified by the operator. The setting unit allocates the position of the first terminal which is included in the position information of the first terminal to the symbol which is indicative of the device which has been detected by the operation detection unit.

Abstract: The memory error determination device includes a processor configured to: detect a memory element in which an error has occurred in each of a plurality of layers included in a memory being three-dimensionally stacked, specify a position of each memory element in which the error has occurred in each of the plurality of layers, and determine that, when the position of each memory element in which the error has occurred is linearly aligned across a predetermined number of layers among the plurality of layers, the predetermined number being two or more, an error that has occurred in the memory is a soft error due to radiation incident on the memory.

Abstract: The program generation apparatus includes a terminal detection unit for detecting position information including a position of a first terminal of an input/output apparatus to which an electrical wiring is connected. A display control unit displays, on a display part, a control program and position information of the first terminal detected by the terminal detection unit. The operation detection unit detects a symbol indicating the device specified. by the operator. The setting unit allocates the position of the first terminal which is included in the position. information of the first terminal to the symbol which is indicative of the device which has been detected by the operation detection unit.

Abstract: To enable adjustment of digital filters suited to disturbances occurring in the surroundings. A receiving device includes: a digital filter that eliminates or attenuates a disturbance included in a signal received through a communication line; a coefficient adjusting unit that adjusts a coefficient of the digital filter based on operation schedule information of a device causing the disturbance in the communication line; and an information table that records a combination of operation information included in the operation schedule information and a coefficient of the digital filter corresponding to the operation information or correction information of the coefficient, in which the coefficient adjusting unit calculates the coefficient of the digital filter or the correction information of the coefficient from the information table based on the operation information included in the operation schedule information, and adjusts the coefficient of the digital filter.

Abstract: A machine tool system is equipped with a machine tool and a controller. The machine tool is equipped with a machine tool body and at least one temperature sensor that acquires temperature data of the machine tool body. The controller is equipped with a storage that stores the temperature data acquired in time-series by the temperature sensor, and an auxiliary power supply that supplies power to the temperature sensor and the storage when the supply of power to the machine tool body is stopped. The controller controls the machine tool by using the temperature data over a predetermined time range stored in the storage, and selects, in response to a charge state of the auxiliary power supply, the temperature data to be used in first control after the supply of power to the machine tool body is resumed.

Abstract: Provided are a circuit configuration optimization apparatus and a machine learning device capable of reducing the occurrence frequency of a malfunction based on one of the current position and the current time of a FPGA device. The circuit configuration optimization apparatus includes: a state data acquisition section that acquires at least one of a current position and current time of the FPGA device as state data; and a circuit configuration determination section that determines a circuit configuration of the FPGA device based on the state data acquired by the state data acquisition section, and outputs a command value for reconfiguring the determined circuit configuration on the FPGA device.

Abstract: A storage unit stores first information on at least one of a machine tool and a peripheral device of the machine tool. A control unit includes a generation unit configured to generate a first light emitting pattern which is recognizable to human eyes and which includes a lighting-on state, a lighting-off state, or a lighting-on/off state of a light emitting element, a modulation unit configured to modulate the first information into a light communication signal based on lighting-on/off of the light emitting element unrecognizable to human eyes but recognizable to an electronic device, a superimposition unit configured to superimpose the light communication signal on the first light emitting pattern, thereby generating a second light emitting pattern including the light communication signal, and a light emitting element control unit configured to control the light emitting element on a basis of the second light emitting pattern generated by the superimposition unit.

Abstract: A circuit configuration optimization apparatus includes a machine learning device that learns a circuit configuration of a FPGA device. The machine learning device observes circuit configuration data of the FPGA device and FPGA error occurrence state data indicating an error occurrence state of the FPGA device as state variables that express a current state of an environment. In addition, the machine learning device acquires determination data indicating propriety determination results of an operating state of the FPGA device. Then, the machine learning device learns the circuit configuration of the FPGA device in association with the FPGA error occurrence state data, using the state variables and the determination data.

Abstract: A storage unit stores first information on at least one of a machine tool and a peripheral device of the machine tool. A control unit includes a generation unit configured to generate a first light emitting pattern which is recognizable to human eyes and which includes a lighting-on state, a lighting-off state, or a lighting-on/off state of a light emitting element, a modulation unit configured to modulate the first information into a light communication signal based on lighting-on/off of the light emitting element unrecognizable to human eyes but recognizable to an electronic device, a superimposition unit configured to superimpose the light communication signal on the first light emitting pattern, thereby generating a second light emitting pattern including the light communication signal, and a light emitting element control unit configured to control the light emitting element on a basis of the second light emitting pattern generated by the superimposition unit.

Abstract: A circuit configuration optimization apparatus includes a machine learning device that learns a circuit configuration of a FPGA device. The machine learning device observes circuit configuration data of the FPGA device and FPGA error occurrence state data indicating an error occurrence state of the FPGA device as state variables that express a current state of an environment. In addition, the machine learning device acquires determination data indicating propriety determination results of an operating state of the FPGA device. Then, the machine learning device learns the circuit configuration of the FPGA device in association with the FPGA error occurrence state data, using the state variables and the determination data.

Abstract: Provided are a circuit configuration optimization apparatus and a machine learning device capable of reducing the occurrence frequency of a malfunction based on one of the current position and the current time of a FPGA device. The circuit configuration optimization apparatus includes: a state data acquisition section that acquires at least one of a current position and current time of the FPGA device as state data; and a circuit configuration determination section that determines a circuit configuration of the FPGA device based on the state data acquired by the state data acquisition section, and outputs a command value for reconfiguring the determined circuit configuration on the FPGA device.

Abstract: An I/O control system includes a numerical controller, amplifiers that drive motors, and an I/O control unit that is connected to a peripheral device. The I/O control unit includes an arithmetic processing unit that generates control information for control over the peripheral device from servo control information received through a communication interface and input data received from the peripheral device through an I/O interface and that outputs the generated control information to the peripheral device through the I/O interface.

Abstract: An I/O control system includes a numerical controller, amplifiers that drive motors, and an I/O control unit that is connected to a peripheral device. The I/O control unit includes an arithmetic processing unit that generates control information for control over the peripheral device from servo control information received through a communication interface and input data received from the peripheral device through an I/O interface and that outputs the generated control information to the peripheral device through the I/O interface.