Patents by Inventor Kenichiro Nagatomo

Kenichiro Nagatomo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240087433
    Abstract: A lighting system includes a plurality of lighting devices and a control device. The plurality of lighting devices are installed in a facility. The control device controls the plurality of lighting devices. The control device controls lighting light projected by at least one lighting device, belonging to the plurality of lighting devices, into colored lighting light, of which a color is different from a color white, to give, upon acquiring information about an event in question, a sign depending on the event in question.
    Type: Application
    Filed: January 22, 2022
    Publication date: March 14, 2024
    Inventors: Takanori AKETA, Kenichiro TANAKA, Jin YOSHIZAWA, Shingo NAGATOMO, Kazuki KITAMURA, Tatsuya TAKAHASHI, Tatsuo KOGA, Tomonori YAMADA, Kazuto URA
  • Patent number: 10433420
    Abstract: A circuit board device includes: a printed wiring board; an IC chip provided on an obverse surface of the board and having at least one ground terminal; and a wiring pattern, disposed on the board, for providing a ground potential to the ground terminal of the IC chip. The wiring pattern is disposed on a reverse surface of the printed wiring board. The circuit board device has at least one via that is connected to the wiring pattern and passes through the printed wiring board at a position within a region where the IC chip is mounted on the obverse surface of the printed wiring board.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: October 1, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Kentaro Toda, Kenji Arai, Manabu Miyazawa, Kenichiro Nagatomo, Toru Ueno, Tsuguto Maruko, Hirofumi Ogawa, Tetsuo Oomori
  • Publication number: 20190261507
    Abstract: A circuit board device includes: a printed wiring board; an IC chip provided on an obverse surface of the board and having at least one ground terminal; and a wiring pattern, disposed on the board, for providing a ground potential to the ground terminal of the IC chip. The wiring pattern is disposed on a reverse surface of the printed wiring board. The circuit board device has at least one via that is connected to the wiring pattern and passes through the printed wiring board at a position within a region where the IC chip is mounted on the obverse surface of the printed wiring board.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 22, 2019
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Kentaro TODA, Kenji ARAI, Manabu MIYAZAWA, Kenichiro NAGATOMO, Toru UENO, Tsuguto MARUKO, Hirofumi OGAWA, Tetsuo OOMORI
  • Patent number: 10375819
    Abstract: A circuit board device includes: a printed wiring board; an IC chip provided on an obverse surface of the board and having at least one ground terminal; and a wiring pattern, disposed on the board, for providing a ground potential to the ground terminal of the IC chip. The wiring pattern is disposed on a reverse surface of the printed wiring board. The circuit board device has at least one via that is connected to the wiring pattern and passes through the printed wiring board at a position within a region where the IC chip is mounted on the obverse surface of the printed wiring board.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: August 6, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Kentaro Toda, Kenji Arai, Manabu Miyazawa, Kenichiro Nagatomo, Touru Ueno, Tsuguto Maruko, Hirofumi Ogawa, Tetsuo Oomori
  • Publication number: 20180242444
    Abstract: A circuit board device includes: a printed wiring board; an IC chip provided on an obverse surface of the board and having at least one ground terminal; and a wiring pattern, disposed on the board, for providing a ground potential to the ground terminal of the IC chip. The wiring pattern is disposed on a reverse surface of the printed wiring board. The circuit board device has at least one via that is connected to the wiring pattern and passes through the printed wiring board at a position within a region where the IC chip is mounted on the obverse surface of the printed wiring board.
    Type: Application
    Filed: February 20, 2018
    Publication date: August 23, 2018
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Kentaro TODA, Kenji ARAI, Manabu MIYAZAWA, Kenichiro NAGATOMO, Touru UENO, Tsuguto MARUKO, Hirofumi OGAWA, Tetsuo OOMORI
  • Patent number: 7351342
    Abstract: An aqueous solution containing a fluorine-containing emulsifier in a low concentration of at least 1 ppm by mass and at most 1% by mass (e.g., coagulation waste water after an emulsion polymerization of a fluoropolymer and/or an aqueous solution obtained by washing with an aqueous solution a waste gas from a drying process and/or a heat treating process of the fluoropolymer) is subjected to vacuum concentration under a pressure of at most 100 kPa and a temperature of the aqueous solution of at most 100° C. by means of a heating tube surface evaporation type concentrator equipped with a heat pump or the like, and the fluorine-containing emulsifier is recovered from a highly concentrated aqueous solution containing the fluorine-containing emulsifier in a higher concentration of at least 5% by mass. According to the present method, the fluorine-containing emulsifier can be recovered with a high yield from a low-concentration liquid such as coagulation waste water of a fluoropolymer.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: April 1, 2008
    Assignees: Asahi Glass Company, Limited, Sasakura Engineering Co., Ltd.
    Inventors: Hiroshi Funaki, Koichi Yanase, Hiroki Kamiya, Masao Uehara, Kenichiro Nagatomo, Yasushi Nishimura, Shiro Ohno, Satoru Hirano
  • Patent number: 7159057
    Abstract: An evaluation chip is disclosed whose interrupt priority order can be changed freely. A plurality of interrupt priority order determining circuits 20-1 to 2-4 perform a logical operation on a plurality of signals S11 to S14 used for interrupt priority order modifying control that are applied from outside and a plurality of interrupt signals S31-1 to S31-4, and output interrupt modifying signals S24-1 to S24-4. A plurality of interrupt modules 30-1 to 30-4 perform a logical AND operation on the plurality of signals S24-1 to S24-4 and a plurality of interrupt request signals S15-1 to S15-4 that are applied from outside, and output the signals S31-1 to S31-4. An address generating circuit 40 encodes the plurality of signals S31-1 to S31-4 and generates interrupt vector addresses 40. A microcomputer core 50 executes interrupt instructions that have been fetched from an external program memory 100, based on the addresses S40.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: January 2, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hiroshi Yamasaki, Kenichiro Nagatomo
  • Publication number: 20050216636
    Abstract: An evaluation chip is disclosed whose interrupt priority order can be changed freely. A plurality of interrupt priority order determining circuits 20-1 to 2-4 perform a logical operation on a plurality of signals S11 to S14 used for interrupt priority order modifying control that are applied from outside and a plurality of interrupt signals S31-1 to S31-4, and output interrupt modifying signals S24-1 to S24-4. A plurality of interrupt modules 30-1 to 30-4 perform a logical AND operation on the plurality of signals S24-1 to S24-4 and a plurality of interrupt request signals S15-1 to S15-4 that are applied from outside, and output the signals S31-1 to S31-4. An address generating circuit 40 encodes the plurality of signals S31-1 to S31-4 and generates interrupt vector addresses 40. A microcomputer core 50 executes interrupt instructions that have been fetched from an external program memory 100, based on the addresses S40.
    Type: Application
    Filed: November 16, 2004
    Publication date: September 29, 2005
    Applicant: Oki Electric Co., Ltd.
    Inventors: Hiroshi Yamasaki, Kenichiro Nagatomo
  • Publication number: 20050150833
    Abstract: An aqueous solution containing a fluorine-containing emulsifier in a low concentration of at least 1 ppm by mass and at most 1% by mass (e.g., coagulation waste water after an emulsion polymerization of a fluoropolymer and/or an aqueous solution obtained by washing with an aqueous solution a waste gas from a drying process and/or a heat treating process of the fluoropolymer) is subjected to vacuum concentration under a pressure of at most 100 kPa and a temperature of the aqueous solution of at most 100° C. by means of a heating tube surface evaporation type concentrator equipped with a heat pump or the like, and the fluorine-containing emulsifier is recovered from a highly concentrated aqueous solution containing the fluorine-containing emulsifier in a higher concentration of at least 5% by mass. According to the present method, the fluorine-containing emulsifier can be recovered with a high yield from a low-concentration liquid such as coagulation waste water of a fluoropolymer.
    Type: Application
    Filed: December 16, 2004
    Publication date: July 14, 2005
    Applicants: ASAHI GLASS COMPANY LIMITED, SASAKURA ENGINEERING CO., LTD.
    Inventors: Hiroshi Funaki, Koichi Yanase, Hiroki Kamiya, Masao Uehara, Kenichiro Nagatomo, Yasushi Nishimura, Shiro Ohno, Satoru Hirano