Patents by Inventor Kenichiro Shiozawa

Kenichiro Shiozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6603163
    Abstract: A semiconductor device having a capacitor and a method of manufacturing thereof are provided, securing a certain capacitance while allowing the size to be reduced. The semiconductor device includes a capacitor lower electrode having an upper surface and including a metal film, a dielectric film deposited on the upper surface of the capacitor lower electrode and having its thickness smaller than that of the capacitor lower electrode, and a capacitor upper electrode deposited on the dielectric film, having its width smaller than that of the capacitor lower electrode and including a metal film.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: August 5, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsunobu Hori, Takeshi Matsunuma, Kenichiro Shiozawa, Moriaki Akazawa
  • Publication number: 20030067053
    Abstract: A semiconductor device having a capacitor and a method of manufacturing thereof are provided, securing a certain capacitance while allowing the size to be reduced. The semiconductor device includes a capacitor lower electrode having an upper surface and including a metal film, a dielectric film deposited on the upper surface of the capacitor lower electrode and having its thickness smaller than that of the capacitor lower electrode, and a capacitor upper electrode deposited on the dielectric film, having its width smaller than that of the capacitor lower electrode and including a metal film.
    Type: Application
    Filed: October 30, 2002
    Publication date: April 10, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Katsunobu Hori, Takeshi Matsunuma, Kenichiro Shiozawa, Moriaki Akazawa
  • Publication number: 20030054629
    Abstract: A first interconnection is formed in a first interlayer insulating film. An etching stopper film is formed on the first interconnection. On the etching stopper film, a second interlayer insulating film and an anti-reflective coating are successively formed, and a via hole penetrating the second interlayer insulating film and the anti-reflective coating to reach the etching stopper film is formed. An organic film is formed in the via hole, and a trench reaching the organic film is formed in the second insulating film. By removing the anti-reflective coating and the etching stopper film at the bottom portion of the via hole, a portion of the surface of the first interconnection is exposed, and a second interconnection is formed in the trench and the via hole.
    Type: Application
    Filed: May 15, 2002
    Publication date: March 20, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kenji Kawai, Kenichiro Shiozawa, Yusuke Nakajima
  • Publication number: 20020076894
    Abstract: A semiconductor device having a capacitor and a method of manufacturing thereof are provided, securing a certain capacitance while allowing the size to be reduced. The semiconductor device includes a capacitor lower electrode having an upper surface and including a metal film, a dielectric film deposited on the upper surface of the capacitor lower electrode and having its thickness smaller than that of the capacitor lower electrode, and a capacitor upper electrode deposited on the dielectric film, having its width smaller than that of the capacitor lower electrode and including a metal film.
    Type: Application
    Filed: May 17, 2001
    Publication date: June 20, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsunobu Hori, Takeshi Matsunuma, Kenichiro Shiozawa, Moriaki Akazawa
  • Patent number: 5510175
    Abstract: A nonwoven cloth 1 comprising 100% vinal filaments is bonded and fixed with microporous aromatic polysulfone resin 6 incorporating fine through-holes 5 by the steps of; impregnating the nonwoven cloth 1 with an aromatic polysulfone resinous solution 3 prepared by dissolving the aromatic polysulfone resin in an organic solvent, subsequently immersing the cloth 1 impregnated with the aromatic polysulfone resinous solution 3 in a nonsolvent 4 so as to coagulate the aromatic polysulfone resinous solution 3, afterwards washing the cloth 1 with water, and finally drying the cloth 1. The polishing cloth 7 comprises this nonwoven cloth 1 bonded and fixed with the microporous aromatic polysulfone resin 6. Therefore, as far as the polishing cloth 7 is used, the porous structure of the resin is free from being deformed by heat and pressure added to the cloth during the polishing process and clogging of the polishing particles can also be prevented.
    Type: Grant
    Filed: March 1, 1995
    Date of Patent: April 23, 1996
    Assignee: Chiyoda Co., Ltd.
    Inventor: Kenichiro Shiozawa
  • Patent number: 4954141
    Abstract: A polishing pad for a semiconductor wafer, which pad is made of a foamed fluorine-contained resin sheet and is highly resistant to a corrosive polishing solution such as bromine-methanol system or bromine-methanol-silica powder system.
    Type: Grant
    Filed: January 25, 1989
    Date of Patent: September 4, 1990
    Assignees: Showa Denko Kabushiki Kaisha, Chiyoda Kaushiki Kaisha
    Inventors: Masahiro Takiyama, Kunihiro Miyazaki, Kenichiro Shiozawa