Abstract: A semiconductor device having an ESD protection element with an improved ESD resistance is obtainable even if it is formed on the same substrate together with an internal circuit. An SiGe-P well region (3) mainly composed of SiGe having a smaller breakdown field than Si, is formed in the upper portion of a P type Si substrate (1). A drain region (4) and a source region (5) are selectively formed in the surface of the SiGe-P well region (3), and therefore, the boundary between the SiGe-P well region (3) and the drain and source regions (4), (5) defines a PN junction. This results in an MOS transistor for protection comprising the SiGe-P well region (3), the drain region (4), the source region (5), a gate oxide film (6), and a gate polysilicon layer (7).

Abstract: An object of the present invention is to provide a measuring device and a measuring method capable of determining the number of averaging (the number of measurements automatically made in the measuring device) in the measuring device performing averaging process (automatically making plural measurements on a certain characteristic amount of a sample, and performing a process such as weight assignment, thereby obtaining an average value of measured results obtained from the plural measurements and outputting the average value as the measured result of the sample) while maintaining compatibleness of required measuring accuracy and efficiency in measurements.

Abstract: A method of simulating a memory transistor is provided. An Id-Vcg characteristic is obtained by actual measurement in Step s2, and an Id-Vfg characteristic is obtained by actual measurement in Step s4. Based on the obtained Id-Vcg and Id-Vfg characteristics, the value of a capacitance (Cfc) for use in circuit simulation of the memory transistor is determined in Step s5. In Step s14, the circuit simulation is performed using the value of the capacitance (Cfc) determined in Step s5. This allows a simulated value to reliably approach a measured value since the determined capacitance (Cfc) is based on a result of actual measurement of the characteristics of the memory transistor.

Abstract: A block dividing means (2) receives an original netlist (D1) defining a circuit to be simulated, selects a to-be-analyzed block specifying a device included in the circuit to be simulated based on input parameters provided from a parameter input means (1), divides the selected to-be-analyzed block into a plurality of to-be-analyzed sub-blocks, establishes an electric connection between the plurality of to-be-analyzed sub-blocks so as to provide a circuit configuration equivalent to the to-be-analyzed block, and finally outputs a modified netlist (D2) defining a new circuit to be simulated in which the to-be-analyzed block is replaced with the plurality of to-be-analyzed sub-blocks. A circuit simulation means (3) performs a circuit simulation on the new circuit to be simulated which is defined by the modified netlist (D2). A device for and method of simulation provides a simulation result which reflects the shape of the device in a short period of calculation time.

Abstract: An authentication signal extraction part measures the frequency spectrum of electric noise specific to a semiconductor element for authentication so that a code depending on this frequency spectrum is generated as an authentication signal. An authentication signal storage part previously registers the authentication signal. When performing authentication, the authentication signal generated from the authentication signal extraction part is compared with a registered authentication signal stored in the authentication signal storage part so that a result display part displays successful authentication when coincidence is recognized. Thus, authentication is performed without forming a nonvolatile memory or writing the authentication signal.

Abstract: An object of the present invention is to provide a measuring device and a measuring method capable of determining the number of averaging (the number of measurements automatically made in the measuring device) in the measuring device performing averaging process (automatically making plural measurements on a certain characteristic amount of a sample, and performing a process such as weight assignment, thereby obtaining an average value of measured results obtained from the plural measurements and outputting the average value as the measured result of the sample) while maintaining compatibleness of required measuring accuracy and efficiency in measurements.

Abstract: The number (Nc) of conductor regions and the number (Ncell(i)) of cells constituting each conductor region (ci) are calculated from the result of a configuration simulation. Each conductor region (ci) is judged whether or not the number (Ncell(i)) of cells thereof is less than a minimum cell count (Ncellmin) for recognition as an electrode or interconnect line. A conductor region (ci) judged that the number (Ncell(i)) of cells is not less than the minimum cell count (Ncellmin) is regarded as the electrode or interconnect line. A conductor region (ci) judged that the number (Ncell(i)) of cells is less than the minimum cell count (Ncellmin) is replaced with a dielectric positioned on a previously set one of the top, bottom, left-hand, right-hand, front and rear sides of the conductor region (ci).

Abstract: A semiconductor device having an ESD protection element with an improved ESD resistance is obtainable even if it is formed on the same substrate together with an internal circuit. An SiGe—P well region (3) mainly composed of SiGe having a smaller breakdown field than Si, is formed in the upper portion of a P type Si substrate (1). A drain region (4) and a source region (5) are selectively formed in the surface of the SiGe—P well region (3), and therefore, the boundary between the SiGe—P well region (3) and the drain and source regions (4), (5) defines a PN junction. This results in a MOS transistor for protection comprising the SiGe—P well region (3), the drain region (4), the source region (5), a gate oxide film (6), and a gate polysilicon layer (7).

Abstract: A method of manufacturing a semiconductor device wherein the device is manufactured according to extracted process parameters. The process parameters are extracted as a set of optimum process parameters which satisfy an intended specification using process functions. The process functions describe a characteristic of the semiconductor device, and are determined using experimental values and/or simulated values. The process parameters may then be transmitted online to a factory.

Abstract: In a method and apparatus for device simulation, a correct impact ionization coefficient is calculated from a distribution function by solving Boltzmann transport equation, impact ionization coefficients are calculated by using all candidates of methods of calculating impact ionization coefficients, one of the candidates of methods of calculation capable of providing impact ionization coefficient which can best approximate the correct impact ionization coefficient obtained from the distribution function by solving Boltzmann transport equation is selected, and thereafter, impact ionization coefficients are calculated by using the selected method.