Patents by Inventor Kenichiro Sugio
Kenichiro Sugio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7196937Abstract: A semiconductor integrated circuit has a flash interface for receiving command codes and controlling a flash memory to perform corresponding read, write, and erase operations. The flash interface generates a status signal indicating whether the flash memory is currently being controlled or not. The flash interface includes an address circuit for input and output of flash memory addresses, a status circuit that generates the status signal, and a resetting circuit that resets the status signal to the non-control state according to an address output from the address circuit. This hardware feature is used to halt write operations at the maximum address without the need for a halting command, and to prevent consecutive erasing of the same part of the flash memory.Type: GrantFiled: September 19, 2005Date of Patent: March 27, 2007Assignee: Oki Electric Industry Co., Ltd.Inventor: Kenichiro Sugio
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Patent number: 7072206Abstract: A semiconductor integrated device includes a memory cell holding bit information; a pair of bit lines connected to the memory cell via which the bit information is input and output in predetermined cycles; and an output section that latches an output from the memory cell via one bit line of the pair and the other bit line and outputs the bit information acquired from the one bit line as a result of reading from the memory cell, and which pre-charges the pair of bit lines before access to the memory cell. The memory cell has a cutoff circuit that cuts off the other bit line to hold voltage thereof produced by pre-charging when the bit information held in the memory cell is read out.Type: GrantFiled: March 24, 2005Date of Patent: July 4, 2006Assignee: Oki Electric Industry Co., Ltd.Inventor: Kenichiro Sugio
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Publication number: 20060077721Abstract: A semiconductor integrated circuit has a flash interface for receiving command codes and controlling a flash memory to perform corresponding read, write, and erase operations. The flash interface generates a status signal indicating whether the flash memory is currently being controlled or not. The flash interface includes an address circuit for input and output of flash memory addresses, a status circuit that generates the status signal, and a resetting circuit that resets the status signal to the non-control state according to an address output from the address circuit. This hardware feature is used to halt write operations at the maximum address without the need for a halting command, and to prevent consecutive erasing of the same part of the flash memory.Type: ApplicationFiled: September 19, 2005Publication date: April 13, 2006Applicant: Oki Electric Industry Co., Ltd.Inventor: Kenichiro Sugio
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Publication number: 20050162968Abstract: A semiconductor integrated device which comprises a memory cell 20 holding bit information; a pair of bit lines connected to the memory cell via which the bit information is input and output in predetermined cycles; and an output section 100 that latches an output from the memory cell via one bit line of the pair and the other bit line and outputs the bit information acquired from the one bit line as a result of reading from the memory cell, and which pre-charges the pair of bit lines before access to the memory cell. The memory cell 20 has a cutoff circuit (N24) that cuts off the other bit line to hold voltage thereof produced by pre-charging when the bit information held in the memory cell is read out.Type: ApplicationFiled: March 24, 2005Publication date: July 28, 2005Inventor: Kenichiro Sugio
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Patent number: 6888768Abstract: A semiconductor integrated device which comprises a memory cell 20 holding bit information; a pair of bit lines connected to the memory cell via which the bit information is input and output in predetermined cycles; and an output section 100 that latches an output from the memory cell via one bit line of the pair and the other bit line and outputs the bit information acquired from the one bit line as a result of reading from the memory cell, and which pre-charges the pair of bit lines before access to the memory cell. The memory cell 20 has a cutoff circuit (N24) that cuts off the other bit line to hold voltage thereof produced by pre-charging when the bit information held in the memory cell is read out.Type: GrantFiled: February 3, 2004Date of Patent: May 3, 2005Assignee: Oki Electric Industry Co., Ltd.Inventor: Kenichiro Sugio
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Publication number: 20040240289Abstract: A semiconductor integrated device which comprises a memory cell 20 holding bit information; a pair of bit lines connected to the memory cell via which the bit information is input and output in predetermined cycles; and an output section 100 that latches an output from the memory cell via one bit line of the pair and the other bit line and outputs the bit information acquired from the one bit line as a result of reading from the memory cell, and which pre-charges the pair of bit lines before access to the memory cell. The memory cell 20 has a cutoff circuit (N24) that cuts off the other bit line to hold voltage thereof produced by pre-charging when the bit information held in the memory cell is read out.Type: ApplicationFiled: February 3, 2004Publication date: December 2, 2004Inventor: Kenichiro Sugio
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Patent number: 6643196Abstract: A redundant memory circuit for use in an analog semiconductor memory has a cell array divided into sectors. To replace bad sectors, the cell array may include a pair of redundant sectors disposed at opposite ends of the cell array, or may have a centrally located redundant sector. Alternatively, the redundant memory circuit may have a sector selection circuit that selects the sectors and redundant sector in sequence from one end of the cell array to the other, or may have a word line selector located in the center of the cell array, or may have two cell arrays and a redundant sector selection circuit that enables a bad sector in one cell array to be replaced by a redundant sector in either of the two cell arrays. These arrangements improve the capability for redundancy replacement and the quality of the reproduced analog signal.Type: GrantFiled: January 30, 2002Date of Patent: November 4, 2003Assignee: Oki Electric Industry Co., Ltd.Inventor: Kenichiro Sugio
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Publication number: 20020126550Abstract: A redundant memory circuit for use in an analog semiconductor memory has a cell array divided into sectors. To replace bad sectors, the cell array may include a pair of redundant sectors disposed at opposite ends of the cell array, or may have a centrally located redundant sector. Alternatively, the redundant memory circuit may have a sector selection circuit that selects the sectors and redundant sector in sequence from one end of the cell array to the other, or may have a word line selector located in the center of the cell array, or may have two cell arrays and a redundant sector selection circuit that enables a bad sector in one cell array to be replaced by a redundant sector in either of the two cell arrays. These arrangements improve the capability for redundancy replacement and the quality of the reproduced analog signal.Type: ApplicationFiled: January 30, 2002Publication date: September 12, 2002Inventor: Kenichiro Sugio
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Publication number: 20020017927Abstract: A semiconductor integrated circuit device is comprised of: an internal voltage step-down power supply circuit having a first area generating a predetermined internal power supply voltage and a second area wherein an internal power supply voltage is increased at a predetermined rate in accordance with a rise in an external power supply voltage; an internal circuit operated from an internal power supply generated in the first area of the power supply circuit; a first amplifier which is operated from the internal power supply and receives and amplifies data read from a memory cell; a second amplifier which is operated from an external power supply, and receives and amplifies data of an internal power supply voltage level output from the first amplifier, then converts it to data of an external power supply voltage level; and an output driver which is operated from the external power supply and outputs the data of the external power supply voltage level.Type: ApplicationFiled: June 21, 1999Publication date: February 14, 2002Inventor: KENICHIRO SUGIO
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Patent number: 5825215Abstract: An output buffer circuit of the present invention comprises a first input terminal receiving a first input signal, a second input terminal receiving a second input signal, a control input terminal receiving a control signal, an output terminal outputting an output signal, a first transistor coupled between the output node and a first potential source and a second transistor coupled between the output node and a second potential source. The output buffer of the present invention further includes a first gate circuit and a second gate circuit. The first gate circuit has a first input node coupled to receive the first input signal, a second input node coupled to receive the control signal, an enable input node coupled to receive the second input signal and an output node coupled to the control terminal of the first transistor. The first gate circuit outputs the signal received by the enable input node when the signals received by the first and second input nodes have predetermined level.Type: GrantFiled: February 28, 1997Date of Patent: October 20, 1998Assignee: Oki Electric Industry Co., Ltd.Inventors: Kenichiro Sugio, Tetsuya Mitoma
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Patent number: 5602796Abstract: A word line driver has a decoder for outputting decode signals having first and second logic levels, level shifters for receiving the respective decode signals, each level shifter outputting drive signal having first and third logic levels in response to the received decode signal, the third logic level being higher than the second logic level; a pumping circuit for outputting word line activation signals, at least one of the word line activation signals having the third logic level; and groups of output circuits, each group having the output circuits connected to one of the level shifters and a word line, respectively, each of the output circuits outputting the word line activation signal to the respective word line in response to the decode signal and the drive signal.Type: GrantFiled: October 5, 1994Date of Patent: February 11, 1997Assignee: Oki Electric Industry Co., Ltd.Inventor: Kenichiro Sugio