Patents by Inventor Kenichirou Nakagawa

Kenichirou Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060290709
    Abstract: In an information processing method for processing a user's instruction on the basis of a plurality of pieces of input information which are input by a user using a plurality of types of input modalities, each of the plurality of types of input modalities has a description including correspondence between the input contents and semantic attributes. Each input content is acquired by parsing each of the plurality of pieces of input information which are input using the plurality of types of input modalities, and semantic attributes of the acquired input contents are acquired from the description. A multimodal input integration unit integrates the acquired input contents on the basis of the acquired semantic attributes.
    Type: Application
    Filed: June 1, 2004
    Publication date: December 28, 2006
    Applicant: Canon Kabushiki Kaisha
    Inventors: Hiromi Omi, Makoto Hirota, Kenichirou Nakagawa
  • Publication number: 20060081891
    Abstract: A nonvolatile semiconductor memory includes a gate insulating layer, a control gate layer, a first silicide layer, charge accumulating layers, memory gate layers and second silicide layers. The gate insulating layer is formed on a first region of a semiconductor substrate. The control gate layer is formed on the gate insulating layer. The first silicide layer is formed on the control gate layer. The charge accumulating layer is formed on one side of the first region of the semiconductor substrate, and capable to accumulate charges. The memory gate layers is formed on the charge accumulating layer, away from the control gate layer. The second silicide layer is formed on the memory gate layer. The memory gate layer includes a thick gate layer and a thin gate layer. The thick gate layer is formed far side from the control gate layer, and bonded to the second silicide layer.
    Type: Application
    Filed: October 19, 2005
    Publication date: April 20, 2006
    Inventor: Kenichirou Nakagawa