Patents by Inventor Kenichirou Suetugu

Kenichirou Suetugu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device using lead-free solder as die bonding material and die bonding material not containing lead
    Patent number: 7973412
    Abstract: In a semiconductor device bonded to a motherboard with a bonding material having a melting point of 200° C. to 230° C., a bonding material 15 which is a die bonding material for bonding a semiconductor element 13 to a semiconductor substrate 11 is a Bi alloy containing 0.8 wt % to 10 wt % of Cu and 0.02 wt % to 0.2 wt % of Ge, so that the bonding material 15 for bonding the semiconductor element 13 to the semiconductor substrate 11 is not melted when the semiconductor device is bonded to the motherboard by reflowing. It is therefore possible to suppress poor connection on the semiconductor element 13, thereby securing the mountability and electrical reliability of the semiconductor device.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: July 5, 2011
    Assignee: Panasonic Corporation
    Inventors: Seiji Fujiwara, Yoshihiro Tomita, Akio Furusawa, Kenichirou Suetugu
  • SEMICONDUCTOR DEVICE AND DIE BONDING MATERIAL
    Publication number: 20090166876
    Abstract: In a semiconductor device bonded to a motherboard with a bonding material having a melting point of 200° C. to 230° C., a bonding material 15 which is a die bonding material for bonding a semiconductor element 13 to a semiconductor substrate 11 is a Bi alloy containing 0.8 wt % to 10 wt % of Cu and 0.02 wt % to 0.2 wt % of Ge, so that the bonding material 15 for bonding the semiconductor element 13 to the semiconductor substrate 11 is not melted when the semiconductor device is bonded to the motherboard by reflowing. It is therefore possible to suppress poor connection on the semiconductor element 13, thereby securing the mountability and electrical reliability of the semiconductor device.
    Type: Application
    Filed: December 23, 2008
    Publication date: July 2, 2009
    Applicant: Panasonic Corporation
    Inventors: Seiji Fujiwara, Yoshihiro Tomita, Akio Furusawa, Kenichirou Suetugu