Abstract: A semiconductor device that includes a circuit portion, a first light-shielding film and plural second light-shielding films. In the circuit portion, a plurality of wiring layers that include circuit elements are laminated. The first light-shielding film covers an uppermost layer of the wiring layers and light-shields light that is illuminated at the circuit portion. The second light-shielding films are covered by the first light shielding film and formed so as to respectively encircle the wiring layers in ring forms. Outer peripheries of the plural second light-shielding films are formed to be successively smaller from an upper to a lower layer, so as to be at the inner side relative to the outer periphery of the second light-shielding film of the upper layer.

Abstract: A semiconductor device that includes a circuit portion, a first light-shielding film and plural second light-shielding films. In the circuit portion, a plurality of wiring layers that include circuit elements are laminated. The first light-shielding film covers an uppermost layer of the wiring layers and light-shields light that is illuminated at the circuit portion. The second light-shielding films are covered by the first light shielding film and formed so as to respectively encircle the wiring layers in ring forms. Outer peripheries of the plural second light-shielding films are formed to be successively smaller from an upper to a lower layer, so as to be at the inner side relative to the outer periphery of the second light-shielding film of the upper layer.

Abstract: A determination unit of a power-on reset circuit of a semiconductor integrated circuit is provided that ANDs (1) a first monitoring signal output from a first monitoring unit for monitoring when a first source voltage supplied from outside the semiconductor integrated circuit reaches a predetermined level and (2) a second monitoring signal output from a second monitoring unit for monitoring when an internal source voltage reaches a predetermined level, to produce a reset signal. In the determination unit, a first PMOS is inserted in series with a second PMOS connected between the first source voltage and a node. The conducting state of the second PMOS is controlled by the second monitoring signal. The conducting state of the first PMOS is controlled by the reset signal. Thus, even when the second monitoring signal becomes unstable and the second PMOS and a first NMOS are simultaneously turned on, the first PMOS is turned off, thus causing no flow of through current.

Abstract: An oscillation circuits includes an oscillation unit 30 for generating an internal clock signal having an amplitude of vibration corresponding to an internal power supply voltage thereof, switches 28, 29, a NMOS 13 of a tolerant input circuit, a first-stage driver 15, and a coupling capacitance 27. The switches 28, 29 are turned off when the external clock signal is inputted to a clock terminals 1, 2, and are turned on when the oscillation unit 30 oscillates. The NMOS 13 changes the amplitude of the input clock signal by the on-resistance and the outputs the above input clock signal from the drain electrode. The first-stage driver 15 drives the output of the drain electrode of the NMOS 13 and outputs the output thereof as a clock signal. The coupling capacitance 27 changes the gate voltage of the NMOS 13 when the input clock signal rises so as to keep the above on-resistance constant.

Abstract: In testing the function of an integrated circuit which includes a power voltage regulator for smoothing a power voltage received on an input terminal so as to reach an adjustment target voltage level, and a voltage adjuster for adjusting the voltage level, the voltage adjuster being interconnected to a wiring which is to supply the power voltage of the adjustment target voltage level thus adjusted to internal logics produced by designing in advance for accomplishing a target function, the voltage adjuster is controlled to execute a function test with plural voltage levels, and, based on a result from the function test, the optimal voltage level is selected which is to be supplied to the internal logics. The inherent performance of the regulator circuit is measured without being affected by the parasitic resistances.

Abstract: A determination unit of a power-on reset circuit of a semiconductor integrated circuit is provided that ANDs (1) a first monitoring signal output from a first monitoring unit for monitoring when a first source voltage supplied from outside the semiconductor integrated circuit reaches a predetermined level and (2) a second monitoring signal output from a second monitoring unit for monitoring when an internal source voltage reaches a predetermined level, to produce a reset signal. In the determination unit, a first PMOS is inserted in series with a second PMOS connected between the first source voltage and a node. The conducting state of the second PMOS is controlled by the second monitoring signal. The conducting state of the first PMOS is controlled by the reset signal. Thus, even when the second monitoring signal becomes unstable and the second PMOS and a first NMOS are simultaneously turned on, the first PMOS is turned off, thus causing no flow of through current.

Abstract: An oscillation circuits includes an oscillation unit 30 for generating an internal clock signal having an amplitude of vibration corresponding to an internal power supply voltage thereof, switches 28, 29, a NMOS 13 of a tolerant input circuit, a first-stage driver 15, and a coupling capacitance 27. The switches 28, 29 are turned off when the external clock signal is inputted to a clock terminals 1, 2, and are turned on when the oscillation unit 30 oscillates. The NMOS 13 changes the amplitude of the input clock signal by the on-resistance and the outputs the above input clock signal from the drain electrode. The first-stage driver 15 drives the output of the drain electrode of the NMOS 13 and outputs the output thereof as a clock signal. The coupling capacitance 27 changes the gate voltage of the NMOS 13 when the input clock signal rises so as to keep the above on-resistance constant.