Patents by Inventor Kenji Fujikata

Kenji Fujikata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4748558
    Abstract: A loosely coupled multi-processor system including a plurality of terminals and corresponding processors. When a particular terminal tries to start a program, the corresponding processor sets the largest number of the terminals, which are serviceable, on the basis of the load status of the processors which are permanently watched by the OS (operating system) in a main memory. The processor compares this largest number with the number of terminals, which are in service at that time and when the number of the terminals, which are in service, is smaller than the largest number, processing by the terminal issuing a service demand begins. Alternatively, when the number of the terminals, which are in service, is equal to or greater than the largest number, the processor cannot treat the service demand from the terminal and reports this to a global processor.
    Type: Grant
    Filed: May 1, 1986
    Date of Patent: May 31, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Hirosawa, Kazumitu Kondo, Katsuto Miyazaki, Kenji Fujikata
  • Patent number: 4531119
    Abstract: A method and apparatus for selectively key-inputting a Kanji (Chinese and Japanese ideogram) in a Japanese sentence are disclosed. The operator keys-in a reading of a desired Kanji through a keyboard, and candidate Kanjis for that reading are displayed on a display screen so that the operator chooses a relevant Kanji for entry out of the displayed candidate Kanjis. In entering the reading of a Kanji, blocks which are in correspondence to character keys located in home positions of the keyboard and in the neighborhood thereof are displayed on the display screen and candidate Kanjis corresponding to the reading of the desired Kanji are displayed in the blocks. The operator then keys a character key corresponding to a relevant candidate Kanji displayed on the display screen.
    Type: Grant
    Filed: November 30, 1984
    Date of Patent: July 23, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Nakayama, Masaaki Kurosu, Yoshimitsu Ohshima, Kenji Fujikata, Shigeru Uchida, Akira Nakajima
  • Patent number: 4197486
    Abstract: An electron beam deflection control system includes a first signal generation circuit which generates a triangular signal varying at a comparatively low speed, a second signal generation circuit which generates a stepped signal varying at a comparatively high speed, and a switching arrangement to change over the first and second signal generation circuits and to drive one of them, whereby the signal from the generation circuit selected by the switching arrangement is used as a deflection signal for an electron beam.
    Type: Grant
    Filed: October 14, 1977
    Date of Patent: April 8, 1980
    Assignees: Nippon Telegraph and Telephone Public Corporation, Hitachi, Ltd.
    Inventors: Atsushi Iwata, Minpei Fujinami, Akinori Shibayama, Norio Yokozawa, Kenji Maio, Kenji Fujikata
  • Patent number: 4161700
    Abstract: An analog comparator comprising a generator circuit which generates an input signal voltage having a certain slew rate, a setting circuit which sets a target or desired voltage, another setting circuit which sets a threshold voltage corresponding to the slew rate of the input signal voltage and an ambient temperature, and a comparison circuit which receives the input signal voltage, the target voltage and the threshold voltage and which delivers a coincidence timing signal upon detecting that the input signal voltage has reached a voltage shifting by the threshold voltage from the target voltage.
    Type: Grant
    Filed: November 22, 1977
    Date of Patent: July 17, 1979
    Assignees: Hitachi, Ltd., Nippon Telegraph and Telephone Public Corporation
    Inventors: Kenji Fujikata, Norio Yokozawa, Akinori Shibayama
  • Patent number: 4051457
    Abstract: In a character displaying device having a character pattern memory which is made up of a circulating sequential access memory storing character patterns therein, a character pattern generating system comprises a high speed buffer memory which stores the character codes of one line or any other suitable amount of characters to be displayed and the corresponding character patterns, so that each time one character is delivered as an output from the character pattern memory, the presence of the character code of the particular character is examined for all the character codes of the buffer memory, and the character pattern of the particular character is written into the buffer memory when the character codes are coincident, the writing operations being sequentially executed in the order of the character outputs of the character pattern memory, thereby making it possible to finish all the character patterns in the buffer memory within a period in which the read-out of the character pattern memory circulates.
    Type: Grant
    Filed: February 3, 1976
    Date of Patent: September 27, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Fumiyuki Inose, Kenji Fujikata, Norio Yokozawa