Abstract: The semiconductor memory device includes a plurality of memory cell arrays and a control circuit that outputs a first signal and a second signal. The first signal instructs start of precharging of each memory cell array. The second signal instructs completion of the precharging and transition to a read access. The first signal is wired through one or more delay circuits to arrive at each memory cell array with a time difference, and the second signal is wired not through the one or more delay circuits.

Abstract: A voltage generator for nonvolatile memory that generates an applied voltage to be applied to a nonvolatile memory includes a first voltage generator to generate a first voltage corresponding to the applied voltage, a reference voltage generator to generate a reference voltage, a comparator to compare the first voltage with the reference voltage and output a boost operation control signal according to a comparison result, and a booster to generate the applied voltage in a pulse-like voltage waveform by starting or stopping boost operation based on the boost operation control signal. The applied voltage corresponding to the first voltage upon inversion of the boost operation control signal is varied within one pulse-like voltage waveform by varying one of the first voltage and the reference voltage.

Abstract: The semiconductor memory device includes a plurality of memory cell arrays and a control circuit that outputs a first signal and a second signal. The first signal instructs start of precharging of each memory cell array. The second signal instructs completion of the precharging and transition to a read access. The first signal is wired through one or more delay circuits to arrive at each memory cell array with a time difference, and the second signal is wired not through the one or more delay circuits.

Abstract: A conventional layout of power supply protective element cannot sufficiently protect an internal circuit against a surge current that flows into a narrow branch line that branches off from a thick main wiring line. A semiconductor device according to an embodiment of the present invention includes a power supply protective element connected around a terminal; a main wiring line connected with a VCC pad or a GND pad; a branch line that branches off from the main wiring line and applies a power supply potential or a ground potential to a functional block of the semiconductor device; a branching portion at which the branch line branches off from the main wiring line; and an internal power supply protective element connected with the branch line.

Abstract: To provide a semiconductor storage device capable of reducing the number of ECC bits. A semiconductor storage device according to an embodiment of the invention includes a memory cell array, an ECC cell storing ECC bits, and an ECC computating circuit calculating the ECC bits, which calculates first ECC bits as the ECC bits for first data including at least one write data and a part of read data that is read from the memory cell array.

Abstract: A voltage generator for nonvolatile memory that generates an applied voltage to be applied to a nonvolatile memory includes a first voltage generator to generate a first voltage corresponding to the applied voltage, a reference voltage generator to generate a reference voltage, a comparator to compare the first voltage with the reference voltage and output a boost operation control signal according to a comparison result, and a booster to generate the applied voltage in a pulse-like voltage waveform by starting or stopping boost operation based on the boost operation control signal. The applied voltage corresponding to the first voltage upon inversion of the boost operation control signal is varied within one pulse-like voltage waveform by varying one of the first voltage and the reference voltage.

Abstract: A conventional layout of power supply protective element cannot sufficiently protect an internal circuit against a surge current that flows into a narrow branch line that branches off from a thick main wiring line. A semiconductor device according to an embodiment of the present invention includes a power supply protective element connected around a terminal; a main wiring line connected with a VCC pad or a GND pad; a branch line that branches off from the main wiring line and applies a power supply potential or a ground potential to a functional block of the semiconductor device; a branching portion at which the branch line branches off from the main wiring line; and an internal power supply protective element connected with the branch line.

Abstract: To provide a semiconductor storage device capable of reducing the number of ECC bits. A semiconductor storage device according to an embodiment of the invention includes a memory cell array, an ECC cell storing ECC bits, and an ECC computating circuit calculating the ECC bits, which calculates first ECC bits as the ECC bits for first data including at least one write data and a part of read data that is read from the memory cell array.

Abstract: A semiconductor memory device includes: a memory cell region having main virtual ground lines; and a reference cell region having reference virtual ground lines, and the reference cell region having substantially the same interconnection routine as said memory cell region, wherein, in said reference cell region, adjacent reference cells to a selected reference cell to be referred are off-bit cells.

Abstract: A semiconductor memory device includes: a memory cell region having main virtual ground lines; and a reference cell region having reference virtual ground lines, and the reference cell region having substantially the same interconnection routine as said memory cell region, wherein, in said reference cell region, adjacent reference cells to a selected reference cell to be referred are off-bit cells.

Abstract: A semiconductor memory device includes: a memory cell region having main virtual ground lines; and a reference cell region having reference virtual ground lines, and the reference cell region having substantially the same interconnection routine as the memory cell region, wherein, in the reference cell region, adjacent reference cells to a selected reference cell to be referred are off-bit cells.

Abstract: A semiconductor memory device (100) having an array of ROM cells (101) based on a flat cell architecture has been disclosed. Semiconductor memory device (100) can include a y-selector (103) coupled between a sense amplifier (102) and array (101). During a read operation, the y-selector can electrically connect a selected digit line (D2) and an adjacent digit line (D3) to the sense amplifier. Y-selector (103) can couple a next digit line (D4) to a precharge voltage that may be supplied by a precharge circuit (104). A virtual ground selector (105) can apply a ground voltage level from a main virtual ground line (VG1) to sources of a column of memory cells including a selected memory cell (310). Virtual ground selector (105) can apply a precharge voltage to an adjacent main virtual ground line (VG2). In this manner, a minimum sensing current, when a series of memory cells along a selected word line (W01) are on-bit cells, can be improved.

Abstract: A semiconductor ROM device which enables to obtain a reference current which can securely distinguish data stored in a memory cell in a multilevel mask ROM for storing multilevel data of three or more levels per memory cell. The device comprises a memory cell in which a threshold voltage is set up corresponding to an amount of ions injected to a channel region of a cell transistor and multilevel data of three or more levels are stored, a reference cell for generating the reference current for comparing with a current read out from the memory cell, and dummy cells disposed adjacent to the reference cell. In the channel region of the reference cell and the channel region of the dummy cell, ions are injected simultaneously to set up the equal threshold voltages both in the reference cell and the dummy cell.

Abstract: A semiconductor memory device (100) having an array of ROM cells (101) based on a flat cell architecture has been disclosed. Semiconductor memory device (100) can include a y-selector (103) coupled between a sense amplifier (102) and array (101). During a read operation, the y-selector can electrically connect a selected digit line (D2) and an adjacent digit line (D3) to the sense amplifier. Y-selector (103) can couple a next digit line (D4) to a precharge voltage that may be supplied by a precharge circuit (104). A virtual ground selector (105) can apply a ground voltage level from a main virtual ground line (VG1) to sources of a column of memory cells including a selected memory cell (310). Virtual ground selector (105) can apply a precharge voltage to an adjacent main virtual ground line (VG2). In this manner, a minimum sensing current, when a series of memory cells along a selected word line (WO1) are on-bit cells, can be improved.

Abstract: A semiconductor memory device includes: a memory cell region having main virtual ground lines ; and a reference cell region having reference virtual ground lines, and the reference cell region having substantially the same interconnection routine as said memory cell region, wherein, in said reference cell region, adjacent reference cells to a selected reference cell to be referred are off-bit cells.

Abstract: A semiconductor ROM device which enables to obtain a reference current which can securely distinguish data stored in a memory cell in a multilevel mask ROM for storing multilevel data of three or more levels per memory cell. The device comprises a memory cell in which a threshold voltage is set up corresponding to an amount of ions injected to a channel region of a cell transistor and multilevel data of three or more levels are stored, a reference cell for generating the reference current for comparing with a current read out from the memory cell, and dummy cells disposed adjacent to the reference cell. In the channel region of the reference cell and the channel region of the dummy cell, ions are injected simultaneously to set up the equal threshold voltages both in the reference cell and the dummy cell.

Abstract: It is an object of the present invention to prolong the life, and increase the reliability, of a reference voltage generation circuit which generates word line voltages for use in a mask ROM which uses the multiple-valued technology. The circuit, which uses series-connected P-channel MOS transistors P1, P2, . . . Pm and parallel-connected dummy cell transistors C21, C22, . . . C2n to generate a reference voltage T2V at the node point, has dummy cell transistors C01, C02, . . . C0n, with a threshold value lower than that of the dummy cell transistors C21, C22, . . . C2n, between the output end of the reference voltage T2V and the dummy cell transistors C21, C22, . . . C2n.

Abstract: A voltage generation circuit for a multivalued cell type mask ROM includes partial circuits of the same number as the row number of memory cell transistors. Each of the partial circuits includes a cell part circuit, which includes a memory cell transistor and a resistor, which is formed to have the same resistance as the resistance parasitically added to a source and a drain of a memory cell transistor. Each of the partial circuits is supplied with the same signal as the signal supplied to a corresponding word line, so that the partial circuit corresponding to the word line of a selected memory cell transistor is selected to generate a voltage interlocked with a variation in the threshold caused by a difference between the source potential and the substrate potential.

Abstract: A semiconductor multivalued read only memory device stores multivalued data in a memory cell array and multivalued reference data in reference cell arrays, and stepwise changes word lines and reference word lines to different active levels for reading out the multivalued data and the corresponding multivalued reference data at different timings so as to determine the value of each multivalued datum by comparing it to the multivalued reference data without undesirable influence of deviated threshold and unintentionally deviated active level.

Abstract: In a NOR-type mask ROM, only one of opposite ends of each subsidiary digit line is connected to each block selection MOS transistor. The block selection MOS transistors are alternately connected to one end and the other end of adjacent subsidiary digit lines. Each of the block selection MOS transistors has a source and a drain connected to the primary and the subsidiary digit lines so that a current path at a channel portion has a direction perpendicular to the block selection lines. A gate of each block selection MOS transistor is located directly under the block selection line and has a gate width wider than the width of the subsidiary digit line.