Patents by Inventor Kenji Hirakawa

Kenji Hirakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8323811
    Abstract: A lead acid storage battery according to the present invention comprises a battery container for housing a plurality of cells, a middle lid for covering the battery container, and an upper lid for covering the middle lid, wherein, on the upper surface of the middle lid, a gas discharging port for discharging the gas generated inside of the cell and an electrolyte recirculating port for recirculating the moisture to be discharged along with the gas within the cell are formed as corresponding to each cell. A plurality of exhaust chambers separated by an exhaust chamber partition are formed in a space surrounded by the middle lid and the upper lid, and a mechanism for collectively exhausting the gas discharged from the gas discharging port to the outside of the battery by interconnecting the plurality of exhaust chambers is comprised.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: December 4, 2012
    Assignee: GS Yuasa International Ltd.
    Inventors: Kazuma Saito, Kenji Hirakawa, Motoshi Kiribayashi
  • Patent number: 8257856
    Abstract: To improve the penetration short-circuit resistance of a valve-regulated lead-acid battery. A mixed and scooped mat of glass fibers and organic fibers is used as a separator 3 of a battery comprising an electrode plate pack 4 obtained by inserting the separator 3 between a positive electrode plate 2 and a negative electrode plate 1 and housed in a container 5 and an electrolyte retained in the electrode plate pack 4 and the separator 3, wherein the separator is a mixed and scooped mat of glass fibers and organic fibers and the electrolyte is silica sol mixed with silica and silica sol is injected as the electrolyte.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: September 4, 2012
    Assignee: GS Yuasa International Ltd.
    Inventors: Kazuma Saito, Kenji Hirakawa
  • Publication number: 20090325040
    Abstract: A lead acid storage battery according to the present invention comprises a battery container for housing a plurality of cells, a middle lid for covering the battery container, and an upper lid for covering the middle lid, wherein, on the upper surface of the middle lid, a gas discharging port for discharging the gas generated inside of the cell and an electrolyte recirculating port for recirculating the moisture to be discharged along with the gas within the cell are formed as corresponding to each cell. A plurality of exhaust chambers separated by an exhaust chamber partition are formed in a space surrounded by the middle lid and the upper lid, and a mechanism for collectively exhausting the gas discharged from the gas discharging port to the outside of the battery by interconnecting the plurality of exhaust chambers is comprised.
    Type: Application
    Filed: August 3, 2007
    Publication date: December 31, 2009
    Inventors: Kazuma Saito, Kenji Hirakawa, Motoshi Kiribayashi
  • Publication number: 20080199769
    Abstract: To improve the penetration short-circuit resistance of a valve-regulated lead-acid battery. A mixed and scooped mat of glass fibers and organic fibers is used as a separator 3 of a battery comprising an electrode plate pack 4 obtained by inserting the separator 3 between a positive electrode plate 2 and a negative electrode plate 1 and housed in a container 5 and an electrolyte retained in the electrode plate pack 4 and the separator 3, wherein the separator is a mixed and scooped mat of glass fibers and organic fibers and the electrolyte is silica sol mixed with silica and silica sol is injected as the electrolyte.
    Type: Application
    Filed: February 19, 2008
    Publication date: August 21, 2008
    Applicant: GS YUASA CORPORATION
    Inventors: Kazuma Saito, Kenji Hirakawa
  • Patent number: 7272460
    Abstract: A method for designing a manufacturing process of an electronic device includes calibrating a technology computer-aided design system by fitting simulation parameters of manufacturing process and electrical characteristic simulations, using first feature of commercial manufacturing process of first electronic device manufactured by first manufacturing facilities, and first electrical characteristic of the first electronic device; acquiring second feature of trial manufacturing process of second electronic device manufactured by second manufacturing facilities, and second electrical characteristic of the second electronic device; calculating simulation electrical characteristic of the second electronic device by substituting the second feature to the manufacturing process simulation corresponding to the trial manufacturing process; comparing the second electrical characteristic with the simulation electrical characteristic; and creating design specification of commercial manufacturing process of the second man
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: September 18, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Akiyama, Masahiro Abe, Kenji Hirakawa, Shigeru Komatsu
  • Publication number: 20050113951
    Abstract: A method for designing a manufacturing process of an electronic device includes calibrating a technology computer-aided design system by fitting simulation parameters of manufacturing process and electrical characteristic simulations, using first feature of commercial manufacturing process of first electronic device manufactured by first manufacturing facilities, and first electrical characteristic of the first electronic device; acquiring second feature of trial manufacturing process of second electronic device manufactured by second manufacturing facilities, and second electrical characteristic of the second electronic device; calculating simulation electrical characteristic of the second electronic device by substituting the second feature to the manufacturing process simulation corresponding to the trial manufacturing process; comparing the second electrical characteristic with the simulation electrical characteristic; and creating design specification of commercial manufacturing process of the second man
    Type: Application
    Filed: September 3, 2004
    Publication date: May 26, 2005
    Inventors: Tatsuo Akiyama, Masahiro Abe, Kenji Hirakawa, Shigeru Komatsu
  • Patent number: 5204276
    Abstract: In the method of manufacturing a semiconductor device, a buffer oxide film, an oxidation-resistant film and a first poly-Si film containing a p-type impurity are successively formed to form a laminate structure on the n-type collector region, followed by forming a protective oxide film by CVD. Then, an opening portion reaching the oxidation-resistant film is formed, followed by forming a second protective insulation film to cover the surface of the first poly-Si film exposed at the side wall of the opening portion. The oxidation-resistant film is excessively etched using the protective insulation films as an etching mask so as to expose the buffer oxide film and to form a bore below the first poly-Si film. The exposed buffer oxide film is removed, followed by filling the bore with a second poly-Si film. Then, a heat treatment is performed under an oxidative atmosphere to form a thermal oxide film covering the surface of the second poly-Si film.
    Type: Grant
    Filed: January 24, 1991
    Date of Patent: April 20, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroomi Nakajima, Nobuyuki Itoh, Hiroyuki Nihira, Eiryo Tsukioka, Kenji Hirakawa, Shin-ichi Taka, Hideki Takada, Yasuhiro Katsumata, Toshio Yamaguchi
  • Patent number: 5086005
    Abstract: In a self-alignment type-lateral bipolar transistor and a manufacturing method thereof, the base width is determined not by the image resolution limit of the lithography technique, as in the prior art, but by the impurity diffusion from the polysilicon layer 118. Therefore, the self-alignment type lateral-structure pnp bipolar transistor and the manufacturing method permit the base width to be as small as possible, resulting in improvement of frequency characteristics, and reducing the size of the transistor element.
    Type: Grant
    Filed: June 5, 1990
    Date of Patent: February 4, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenji Hirakawa
  • Patent number: 5065210
    Abstract: A lateral transistor with a fine structure includes a semiconductor substrate of one conductivity type on which a mesa-shaped projection of opposite conductivity type is provided. The projection has side walls opposed to each other and serves as a collector region. A base region of one conductivity type is provided in one side wall of the projection, while a collector contact region is provided in the other side wall thereof. An emitter region of opposite conductivity type is also formed in the base region. A base contact layer of polysilicon is provided on a field oxide layer and is in contact with the base region at the edge. In the same manner, a collector contact layer of polysilicon provided on the field oxide layer is in contact with the collector contact region at the edge.
    Type: Grant
    Filed: July 5, 1990
    Date of Patent: November 12, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenji Hirakawa
  • Patent number: 5028550
    Abstract: In a method of manufacturing a semiconductor device, when contact holes are to be formed in an insulating film formed on a monocrystalline or polycrystalline semiconductor layer, the contact holes can be formed using a polycrystalline semiconductor layer formed on the insulating film as a mask. Therefore, the lithographic step of forming the contact holes in the insulating film formed on the monocrystalline or polycrystalline semiconductor layer can be eliminated.
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: July 2, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenji Hirakawa
  • Patent number: 4471990
    Abstract: A railroad car wheel is designed to have an amount of displacement of 40 mm or larger, this amount being the amount of displacement of a rim portion relative to a boss portion of the wheel which is the distance between two lines perpendicular to the axis of the wheel, one from the midpoint of the thickness of a plate portion adjacent to ends of curves of the rim fillets and the other from the midpoint of thickness of the plate portion adjacent to ends of curves of the boss fillets.
    Type: Grant
    Filed: December 30, 1982
    Date of Patent: September 18, 1984
    Assignee: Sumitomo Metal Industries, Ltd.
    Inventors: Kenji Hirakawa, Haruo Sakamoto, Shigeru Suzuki, Shigeo Sugawara