Abstract: An output pulse of a flip flop is delayed in a delay inverter circuit before supplied to an input terminal of a level shifter. Then, an output pulse of the next stage flip flop is supplied to a reset terminal of the first flip flop and also to an enable terminal of the level shifter. Further, the level shifter output a sampling pulse with a beginning end equal to the beginning end of the pulse supplied to the input terminal and a terminal and equal to the beginning and of the pulse supplied to the enable terminal. With this arrangement, the subject invention provides a pulse output circuit, a driving circuit for a display device using the pulse output circuit, a display device and a pulse output method, that reduce delay of the terminal end of the pulse in sequentially outputting pulses from plural output terminals.

Abstract: A semiconductor integrated circuit is disclosed which includes: a first D/A converter; a second D/A converter; an amplifier configured to amplify an output of the first D/A converter; an operational amplifier configured to input an output of the second D/A converter; and a selector configured to effect switchover between a normal mode and a test mode, the normal mode being a mode in which the operational amplifier is caused to function as an amplifier for amplifying the output of the second D/A converter, the test mode being a mode in which the operational amplifier is caused to function as a comparator for comparing the output of the second D/A converter with the output of the first D/A converter.

Abstract: An output pulse of a flip flop is delayed in a delay inverter circuit before supplied to an input terminal of a level shifter. Then, an output pulse of the next stage flip flop is supplied to a reset terminal of the first flip flop and also to an enable terminal of the level shifter. Further, the level shifter output a sampling pulse with a beginning end equal to the beginning end of the pulse supplied to the input terminal and a terminal and equal to the beginning and of the pulse supplied to the enable terminal. With this arrangement, the subject invention provides a pulse output circuit, a driving circuit for a display device using the pulse output circuit, a display device and a pulse output method, that reduce delay of the terminal end of the pulse in sequentially outputting pulses from plural output terminals.