Abstract: A semiconductor memory device is described which includes a memory matrix made up of a plurality of memory elements which are arranged in m rows and n columns, a state setting internal signal generator controlled by state setting external signals temporarily applied to a plurality of address lines for converting a signal applied to one of the address lines into two internal signals having a phase difference of one bit period, a column selection decoder, the decoding function thereof being inhibited by a decoding inhibition signal, and a column selection decoder controller inputted with the state setting internal signals and the decoding function inhibition signal for sending a signal to the column selection decoder according to the state setting internal signals for controlling the decoding function of the column selection decoder in two modes.