Abstract: A memory circuit includes a plurality of divided memory cell blocks, a write circuit and a read circuit which connect via a pair of bit lines to each of the divided memory cell blocks. The output of write data to one of the bit line of the write circuit is made to be performed by one system. It is possible to achieve an increase of speed by bit lien division while reducing increase in the memory circuit area accompanying the bit line division.

Abstract: A timing generating circuit generates a control clock (1) and a test clock (2) based on an externally input clock CLK, and outputs the generated clocks to a testing circuit. The control clock (1) is a signal the phase of which is delayed by a predetermined amount with reference to the clock CLK. This predetermined amount can be set/changed with an external test signal. The test clock (2) is nearly an inversion signal of the clock CLK. The testing circuit generates various types of control signals (4) based on either of the clocks (1) and (2), and distributes the signals to a controlling circuit. Which of the clocks (1) and (2) is selected in the testing circuit can be set with an external test signal.

Abstract: A disclosed semiconductor integrated circuit device includes a logic circuit, a memory circuit to which data are written by the logic circuit and from which the data are read by the logic circuit, a register circuit holding the data when the logic circuit writes the data to the memory circuit, and a selector circuit selecting one of data output from the register circuit and data output from the memory circuit, and outputting the selected data to the logic circuit. Further in the semiconductor integrated circuit device, in an operational test of the logic circuit, the selector circuit selects the data output from the register circuit and outputs the selected data to the logic circuit.

Abstract: A disclosed semiconductor integrated circuit device includes a logic circuit, a memory circuit to which data are written by the logic circuit and from which the data are read by the logic circuit, a register circuit holding the data when the logic circuit writes the data to the memory circuit, and a selector circuit selecting one of data output from the register circuit and data output from the memory circuit, and outputting the selected data to the logic circuit. Further in the semiconductor integrated circuit device, in an operational test of the logic circuit, the selector circuit selects the data output from the register circuit and outputs the selected data to the logic circuit.

Abstract: A memory includes a plurality of blocks that each include a plurality of memory cell arrays connected to divided bit lines, a first decoder that generates a block select signal for selecting any of the blocks based on an inputted address signal, read/write portions disposed for the respective blocks, each of the read/write portions executes read or write of the memory cell array belonging to the block of its own, and signal generation portions each generates an operation control signal for bringing the read/write portion that belongs to the selected block into an operating state when the block thereof has been selected by the block select signal. Each of the signal generation portions generates an operation control signal for bringing the read/write portion that belongs to the block thereof into a non-operating state when the block thereof is not selected by the block select signal.

Abstract: A timing generating circuit generates a control clock (1) and a test clock (2) based on an externally input clock CLK, and outputs the generated clocks to a testing circuit. The control clock (1) is a signal the phase of which is delayed by a predetermined amount with reference to the clock CLK. This predetermined amount can be set/changed with an external test signal. The test clock (2) is nearly an inversion signal of the clock CLK. The testing circuit generates various types of control signals (4) based on either of the clocks (1) and (2), and distributes the signals to a controlling circuit. Which of the clocks (1) and (2) is selected in the testing circuit can be set with an external test signal.

Abstract: Pulse generation circuit has a P-MOS transistor having a drain electrode connected to a first power source; a first N-MOS transistor having a drain electrode connected to the source electrode of the P-MOS transistor; a second N-MOS transistor having a drain electrode connected to the source electrode of the first N-MOS transistor, a gate electrode receiving an input pulse signal, and a source electrode connected to the second power source; a delay circuit having an input terminal connected to the source electrode of the P-MOS transistor and the drain electrode of the first N-MOS transistor and an output terminal connected to gate electrode of the P-MOS transistor and gate electrode of the first N-MOS transistor; an inverter input connected to the source electrode of the P-MOS transistor and the drain electrode of the second N-MOS transistor for outputting a generated pulse; and a keeper keeping voltage level to the inverter.

Abstract: There is provided a pulse generation circuit having a small input load and capable of self-reset.

Abstract: The present invention concerns a memory structure wherein a plurality of memory cells such as SRAM are provided in columns and a plurality of bit line pairs are provided for each column. A write circuit drives a first bit line pair and writes data to the memory cells in the column; at the same time, a sense amp reads data by means of the second bit line pair. In that case, the first bit line pair and second bit line pair, provided in the same column, are driven with opposite phase signals. To prevent the reversal of the small potential difference of the second bit line pair for reading at that time, two bit lines, one bit line from the first and second bit line pairs, are arranged parallel in a first wiring layer and are interspersed with a fixed potential wiring. Furthermore, the two other bit lines from the first and second bit line pairs, are arranged parallel in a second wiring layer provided via an insulating layer and are interspersed with a fixed potential wiring.

Abstract: An internal address bus, which is connected between a bus control unit and a memory control unit, is formed by a bidirectional bus. The bidirectional internal address bus is connected to an external address transferring bus which is used to transfer a write address in a system bus to the memory control unit. The bidirectional internal address bus is commonly used for renewal and invalidation of first and second buffers for an instruction cache and operand cache. Therefore, in the present invention, the number of the internal bus lines can be reduced, a control constitution can be simplified, and a consistency of contents in a plurality of internal buffers and the main memory can be easily maintained.