Patents by Inventor Kenji Kanamitsu
Kenji Kanamitsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160133487Abstract: Suppressed is damage of a semiconductor wafer due to charging of a cleaning liquid used in a single wafer type wafer cleaning step. A chemical solution discharged from a tip of a cleaning nozzle is brought into contact with protrusions of wafer chucks to thereby let static electricity of the chemical solution go to the wafer chucks, and subsequently, the cleaning nozzle is moved above the wafer to supply the chemical solution onto a top surface of the wafer, thereby suppressing abnormal discharge (damage) of the wafer due to charging of the chemical solution.Type: ApplicationFiled: January 17, 2016Publication date: May 12, 2016Inventors: Kenji KANAMITSU, Takuya KOGA, Kazutoshi ANABUKI
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Patent number: 9263304Abstract: Suppressed is damage of a semiconductor wafer due to charging of a cleaning liquid used in a single wafer type wafer cleaning step. A chemical solution discharged from a tip of a cleaning nozzle is brought into contact with protrusions of wafer chucks to thereby let static electricity of the chemical solution go to the wafer chucks, and subsequently, the cleaning nozzle is moved above the wafer to supply the chemical solution onto a top surface of the wafer, thereby suppressing abnormal discharge (damage) of the wafer due to charging of the chemical solution.Type: GrantFiled: July 19, 2011Date of Patent: February 16, 2016Assignee: Renesas Electronics CorporationInventors: Kenji Kanamitsu, Takuya Koga, Kazutoshi Anabuki
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Publication number: 20120017948Abstract: Suppressed is damage of a semiconductor wafer due to charging of a cleaning liquid used in a single wafer type wafer cleaning step. A chemical solution discharged from a tip of a cleaning nozzle is brought into contact with protrusions of wafer chucks to thereby let static electricity of the chemical solution go to the wafer chucks, and subsequently, the cleaning nozzle is moved above the wafer to supply the chemical solution onto a top surface of the wafer, thereby suppressing abnormal discharge (damage) of the wafer due to charging of the chemical solution.Type: ApplicationFiled: July 19, 2011Publication date: January 26, 2012Inventors: Kenji KANAMITSU, Takuya KOGA, Kazutoshi ANABUKI
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Publication number: 20110237036Abstract: By ion-implanting an inert gas, for example, nitrogen into a polycrystalline silicon film in an nMIS forming region from an upper surface of the polycrystalline silicon film down to a predetermined depth, an upper portion of the polycrystalline silicon film is converted to an amorphous form to form an amorphous/polycrystalline silicon film. And then, an n-type impurity, for example, phosphorous is ion-implanted into the amorphous/polycrystalline silicon film to form an n-type amorphous/polycrystalline silicon film, the n-type amorphous/polycrystalline silicon film is processed to form a gate electrode having a gate length shorter than 0.1 ?m, a sidewall formed of an insulating film is formed on a side wall of the gate electrode, and a source/drain diffusion layer is formed. Thereafter, a cobalt silicide (CoSi2) layer is formed on an upper portion of the gate electrode by salicide technique.Type: ApplicationFiled: June 7, 2011Publication date: September 29, 2011Inventors: Hiroyuki OHARA, Shino TAKAHASHI, Kenji KANAMITSU, Shuji MATSUO
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Publication number: 20100019324Abstract: By ion-implanting an inert gas, for example, nitrogen into a polycrystalline silicon film in an nMIS forming region from an upper surface of the polycrystalline silicon film down to a predetermined depth, an upper portion of the polycrystalline silicon film is converted to an amorphous form to form an amorphous/polycrystalline silicon film. And then, an n-type impurity, for example, phosphorous is ion-implanted into the amorphous/polycrystalline silicon film to form an n-type amorphous/polycrystalline silicon film, the n-type amorphous/polycrystalline silicon film is processed to form a gate electrode having a gate length shorter than 0.1 ?m, a sidewall formed of an insulating film is formed on a side wall of the gate electrode, and a source/drain diffusion layer is formed. Thereafter, a cobalt silicide (CoSi2) layer is formed on an upper portion of the gate electrode by salicide technique.Type: ApplicationFiled: December 22, 2006Publication date: January 28, 2010Inventors: Hiroyuki Ohara, Shino Takahashi, Kenji Kanamitsu, Shuji Matsuo
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Patent number: 7524729Abstract: A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.Type: GrantFiled: July 27, 2005Date of Patent: April 28, 2009Assignee: Renesas Technology Corp.Inventors: Kenji Kanamitsu, Kouzou Watanabe, Norio Suzuki, Norio Ishitsuka
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Publication number: 20090029524Abstract: A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.Type: ApplicationFiled: October 2, 2008Publication date: January 29, 2009Inventors: Kenji KANAMITSU, Kouzou Watanabe, Norio Suzuki, Norio Ishitsuka
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Publication number: 20080293230Abstract: A silicon-rich oxide (SRO) film is arranged over an uppermost third-level wiring in a semiconductor device. Then, a silicon oxide film and a silicon nitride film lying over the third-level wiring are dry-etched to expose part of the third-level wiring to thereby form a bonding pad and to form an opening over the fuse. In this procedure, the SRO film serves as an etch stopper. This optimizes the thickness of the dielectric films lying over the fuse.Type: ApplicationFiled: July 31, 2008Publication date: November 27, 2008Inventors: Naohiro HOSODA, Kenji Kanamitsu
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Patent number: 7411242Abstract: The object of the present invention is to provide a new nonvolatile semiconductor memory device and its manufacturing method for the purpose of miniaturizing a virtual grounding type memory cell based on a three-layer polysilicon gate, enhancing the performance, and boosting the yield. In a memory cell according to the present invention, a floating gate's two end faces perpendicular to a word line and channel are partly placed over the top of a third gate via a dielectric film. The present invention can reduce the memory cell area of a nonvolatile semiconductor memory device, increase the operating speed, and enhances the yield.Type: GrantFiled: September 30, 2005Date of Patent: August 12, 2008Assignee: Renesas Technology Corp.Inventors: Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Yoshihiro Ikeda, Kenji Kanamitsu
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Patent number: 7358129Abstract: A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.Type: GrantFiled: October 19, 2006Date of Patent: April 15, 2008Assignee: Renesas Technology Corp.Inventors: Keiichi Haraguchi, Masataka Kato, Kenji Kanamitsu
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Patent number: 7303951Abstract: A method of manufacturing a semiconductor device for preventing dielectric breakdown of gate electrodes attributable to needle-like protrusions caused inside a trench in the step of forming element isolation trench in which includes forming a silicon oxide film over a silicon nitride film as an etching mask for forming element isolation trenches, then cleaning the surface of a substrate with a hydrofluoric acid etching solution to lift off obstacles deposited over the surface of the silicon oxide film, before the step of patterning the silicon nitride film by using as a mask a photoresist film provided with an anti-reflection film therebelow.Type: GrantFiled: January 5, 2005Date of Patent: December 4, 2007Assignee: Renesas Technology Corp.Inventors: Kenji Kanamitsu, Takashi Moriyama, Naohiro Hosoda
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Patent number: 7282411Abstract: An AND flash memory of the type wherein a memory cell is constituted of n-type semiconductor regions (a source and a drain) formed in a p-type well of a semiconductor substrate and three gates (including a floating gate, a control gate and a selective gate) is manufactured. In the manufacture, arsenic (As) is introduced into a p-type well in the vicinity of one of side walls of the selective gate to form n-type semiconductor regions (a source and a drain). Thereafter, to cope with a drain disturb problem, the substrate is thermally treated by use of an ISSG (In-Situ Steam Generation) oxidation method so that a first gate, insulating film disposed in the vicinity of one of side walls, at which the n-type semiconductor regions have been formed, is formed thick.Type: GrantFiled: January 18, 2005Date of Patent: October 16, 2007Assignee: Renesas Technology Corp.Inventors: Kenji Kanamitsu, Takashi Moriyama, Naohiro Hosoda, Keiichi Haraguchi, Tetsuo Adachi
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Patent number: 7180788Abstract: A non-volatile semiconductor memory device provides for higher integration by reducing the area of occupation of direct peripheral circuits, in which the memory cell of an AND type flash memory includes a selection gate, a float gate, a control gate that functions as a word line, and an n-type semiconductor region (source, drain) that functions as a local bit line. A pair of local bit lines adjacent to each other in a memory mat are connected with one global bit line at one end in the direction of the column of the memory mat, and a selection MOS transistor, formed by one enhancement type MOS transistor and one depletion type MOS transistor; is connected in series with each of the pair of local bit lines. One of the local bit lines is selected by turning the selection MOS transistor on/off.Type: GrantFiled: January 7, 2005Date of Patent: February 20, 2007Assignee: Renesas Technology Corp.Inventors: Kenji Kanamitsu, Tetsuo Adachi, Masataka Kato, Keiichi Haraguchi
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Publication number: 20070034935Abstract: A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.Type: ApplicationFiled: October 19, 2006Publication date: February 15, 2007Inventors: Keiichi Haraguchi, Masataka Kato, Kenji Kanamitsu
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Patent number: 7126184Abstract: A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.Type: GrantFiled: June 8, 2005Date of Patent: October 24, 2006Assignee: Renesas Technology Corp.Inventors: Keiichi Haraguchi, Masataka Kato, Kenji Kanamitsu
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Publication number: 20060022259Abstract: The object of the present invention is to provide a new nonvolatile semiconductor memory device and its manufacturing method for the purpose of miniaturizing a virtual grounding type memory cell based on a three-layer polysilicon gate, enhancing the performance, and boosting the yield. In a memory cell according to the present invention, a floating gate's two end faces perpendicular to a word line and channel are partly placed over the top of a third gate via a dielectric film. The present invention can reduce the memory cell area of a nonvolatile semiconductor memory device, increase the operating speed, and enhances the yield.Type: ApplicationFiled: September 30, 2005Publication date: February 2, 2006Inventors: Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Yoshihiro Ikeda, Kenji Kanamitsu
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Publication number: 20050269623Abstract: A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.Type: ApplicationFiled: June 8, 2005Publication date: December 8, 2005Inventors: Keiichi Haraguchi, Masataka Kato, Kenji Kanamitsu
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Publication number: 20050260820Abstract: A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.Type: ApplicationFiled: July 27, 2005Publication date: November 24, 2005Inventors: Kenji Kanamitsu, Kouzou Watanabe, Norio Suzuki, Norio Ishitsuka
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Patent number: 6967141Abstract: A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.Type: GrantFiled: August 17, 2004Date of Patent: November 22, 2005Assignee: Renesas Technology Corp.Inventors: Kenji Kanamitsu, Kouzou Watanabe, Norio Suzuki, Norio Ishitsuka
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Publication number: 20050164442Abstract: An AND flash memory of the type wherein a memory cell is constituted of n-type semiconductor regions (a source and a drain) formed in a p-type well of a semiconductor substrate and three gates (including a floating gate, a control gate and a selective gate) is manufactured. In the manufacture, arsenic (As) is introduced into a p-type well in the vicinity of one of side walls of the selective gate to form n-type semiconductor regions (a source and a drain). Thereafter, to cope with a drain disturb problem, the substrate is thermally treated by use of an ISSG (In-Situ Steam Generation) oxidation method so that a first gate,insulating film disposed in the vicinity of one of side walls, at which the n-type semiconductor regions have been formed, is formed thick.Type: ApplicationFiled: January 18, 2005Publication date: July 28, 2005Inventors: Kenji Kanamitsu, Takashi Moriyama, Naohiro Hosoda, Keiichi Haraguchi, Tetsuo Adachi