Patents by Inventor Kenji Kanemitsu

Kenji Kanemitsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor Wafer and Method of Manufacturing the Same and Method of Manufacturing Semiconductor Device
    Publication number: 20110133336
    Abstract: A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes.
    Type: Application
    Filed: February 17, 2011
    Publication date: June 9, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Naotaka Tanaka, Kenji Kanemitsu, Takafumi Kikuchi, Takashi Akazawa
  • Semiconductor wafer and method of manufacturing the same and method of manufacturing semiconductor device
    Patent number: 7897509
    Abstract: A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: March 1, 2011
    Assignee: Renesas Electronics Corp.
    Inventors: Naotaka Tanaka, Kenji Kanemitsu, Takafumi Kikuchi, Takashi Akazawa
  • Semiconductor Wafer and Method of Manufacturing the Same and Method of Manufacturing Semiconductor Device
    Publication number: 20100258948
    Abstract: A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes.
    Type: Application
    Filed: June 25, 2010
    Publication date: October 14, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Naotaka Tanaka, Kenji Kanemitsu, Takafumi Kikuchi, Takashi Akazawa
  • Semiconductor wafer and method of manufacturing the same and method of manufacturing semiconductor device
    Publication number: 20080079152
    Abstract: A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes.
    Type: Application
    Filed: August 10, 2007
    Publication date: April 3, 2008
    Applicant: Renesas Technology Corp.
    Inventors: Naotaka Tanaka, Kenji Kanemitsu, Takafumi Kikuchi, Takashi Akazawa