Abstract: A semiconductor integrated circuit includes a filter and a time-constant detecting circuit. The filter includes resistance elements; capacitance elements, each of which consists of a capacitance-value switching circuit that can vary the capacitance of the capacitance elements and operational amplifiers. The time-constant detecting circuit detects the time constant of the capacitance element and resistance element, which are formed independently of the capacitance elements and resistance elements of the filter. The semiconductor integrated circuit varies the capacitance of the capacitance element in response to the detected time constant to prevent a reduction in the yield by adjusting the cut-off frequency of the filter in spite of variations in manufacturing the resistance elements and capacitance elements of the filter.

Abstract: A filter-equipped semiconductor integrated circuit includes a filter and a time-constant detecting circuit. The filter includes resistance elements; capacitance elements, each of which consists of a capacitance-value switching circuit that can vary the capacitance value of the capacitance element; and operational amplifiers. The time-constant detecting circuit detects the time constant of the capacitance element and resistance element, which are formed independently of the capacitance elements and resistance elements of the filter. The filter-equipped semiconductor integrated circuit varies the capacitance value of the capacitance element in response to the detected time constant so as to prevent the reduction in the yield by adjusting the cut-off frequency of the filter in spite of the manufacturing variations in the resistance elements and capacitance elements of the filter.

Abstract: There is described a charge pump circuit capable of minimizing an offset in a phase difference at the time of zero output current, which would otherwise be caused by variations in elements stemming from variations in a manufacturing process. When a first input signal becomes low, a first MOS transistor is brought into conduction, and an electric current "I1" specified by a second MOS transistor flows to an output node as a charge current. When a second input signal becomes low, a third MOS transistor is brought into conduction, and an electric current "I2" specified by a fourth MOS transistor flows to a current mirror circuit. The current mirror circuit withdraws an electric current "I6"--which is the same as that of the electric current "I2"--from the output node as a discharge current. When the charge or discharge current flows to the output node, there is output an electric current of zero. If there is only the charge current, the charge current flows from the output node.

Abstract: An output circuit 1 has a p-type MOS transistor Q1 connected between a power-voltage node and an output node, and an n-type MOS transistor Q2 connected between a ground-voltage node and the output node. A voltage-current conversion circuit 2 outputs a voltage according to the voltage difference between an input signal and the comparison voltage. According to the output from the voltage-current conversion circuit 2, a signal conversion circuit 3 controls the voltage of the gate electrode of the MOS transistor Q1 with a reference of a second specified voltage, and controls the voltage of the gate electrode of the n-type MOS transistor Q2 with a reference of a first specified voltage.

Abstract: A digital/analog converter including four D/A conversion.The D/A convertor comprises four D/A conversion parts (DA1) to (DA4). On a single semiconductor chip the D/A convertion parts (DA1) to (DA4) are arranged so that the D/A conversion parts (DA1) and (DA3) are symmetric with respect to a first center line (L1), the first and fourth D/A conversion parts (DA1) and (DA4) are arranged symmetric with respect to a second center line (L2) which crosses the first center line (L1) at right angles and the second and third D/A conversion parts are arranged symmetric with respect to the second center line. Although the locations of the resistances of each of the conversion parts produces errors, these cancel each other out due to their arrangement.

Abstract: The present invention is a digital/analog converter which converts a digital signal of a binary number consisting of N.sub.L low-order bits and N.sub.U high-order bits into an analog signal, in which a first digital/analog converting circit driven in accordance with a digital data of low-order bits employs, as conventional, an R-2R system while a second digital/analog converting circuit driven in accordance with a digital data of high-order bits employs a 2R system. As a result, the influence of an error included in the variation in an output of the analog signal which is caused by the variation in the digital data for the least significant bit can be decreased, whereby a high resolution is obtained, keeping a monotonicity, without a high matching of registors.