Abstract: In the synchronous compensator, a load generator loads a bit counter with data in dependence upon whether or not a detection signal from a UW detector falls within the range indicated by an enable signal from a synchronous compensator circuit, thereby excluding the detection signal appearing far from the normal position to establish an appropriate synchronous compensation. The synchronous compensation is thus accomplished on the basis of normally received signal waves without picking up abnormal waves supposed as reflected waves.

Abstract: An improved modulation circuit and method for TDMA are provided, wherein the transmission data (TD) in odd-numbered time-slots are processed based on a transmission-window signal (Twe) with a differential encoder (10o), a timing generator (20o), a filter (30o), an amplitude data generator (40o), a multiplier (50o), and an I/Q-discriminator (60o), which are configured as odd-dedicated units, and is output from an adder (71) as transmission signal data (IT) and (QT). The transmission data (TD) in even-numbered time-slots is processed with a differential encoder (10e) and other components, which are configured as even-dedicated units, and is output from the adder (71) in common. Thereby, the appropriate data transmission can be achieved in spite of a decrease of guard bits between a couple of time-slots.

Abstract: In the synchronous compensator, a load generator loads a bit counter with data in dependence upon whether or not a detection signal from a UW detector falls within the range indicated by an enable signal from a synchronous compensator circuit, thereby excluding the detection signal appearing far from the normal position to establish an appropriate synchronous compensation. The synchronous compensation is thus accomplished on the basis of normally received signal waves without picking up abnormal waves supposed as reflected waves.

Abstract: A descrambler can speed up descrambling and prevent an increase in circuit scale. Received data is descrambled by an EXOR gate that receives a PN pattern signal output from a scramble pattern generator. The data is then converted to parallel data, and the CRC error correction is performed on the parallel data by a 1-bit error corrector. The 160-bit data, on which scrambling is performed is supplied to a parallel EXOR gate. When a PN pattern for descrambling scrambled data is generated by a user scramble pattern generator, the PN pattern output is converted to 160-bit parallel data, and is supplied to the parallel EXOR gate. The 160 EXOR gates descramble the input data bit by bit in parallel.

Abstract: An improved modulation circuit and method for TDMA are provided, wherein the transmission data TD in odd-numbered time-slots are processed based on the transmission-window signal TWe with a differential encoder 10o, a timing generator 20o, a filter 30o, an amplitude data generator 40o, a multiplier 50o and an I/Q-discriminator 60o, which are configured as odd-dedicated units, and is output from an adder 71 as transmission signal data IT and QT. The transmission data TD in even-numbered time-slots is processed with a differential encoder 10e and other components, which are configured as even-dedicated units, and is output from the adder 71 in common. Thereby, the appropriate data transmission can be achieved in spite of the decrease of guard bits between a couple of time-slots.