Abstract: A data bus circuit includes a plurality of data buses, a plurality of data processing units connected to each of the data buses for performing transmission and reception of data in response to a transmission control signal, at least a termination resistor connected to termination of the plurality of data buses, the termination resistor including a first resistance circuit for suppressing reflection of signals on the plurality of data buses upon transmission and reception of data of the plurality of data processing units and a second resistance circuit having a resistance value larger than that of the first resistance circuit, an output control circuit for producing the transmission control signal as to whether the plurality of data processing units perform transmission and reception of data or not, and a changing-over circuit for changing over to connect the first resistance circuit to the data buses through which transmission and reception of data is performed when at least one of the plurality of data proce

Abstract: A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission line itself.

Abstract: A data transfer apparatus transfers data between a source and a destination on a clock having a phase with a signal delay over a connection line taken into account to allow a plurality of destinations to capture the transfer data on the same clock timing. Optimized data transfer and high-speed data transfer are thus realized, which in turn significantly enhances the performance of the data transfer apparatus.