Patents by Inventor Kenji Kawagai

Kenji Kawagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4217505
    Abstract: Disclosed is a monostable multivibrator in which an output voltage of an integrating circuit and a reference voltage from a reference voltage source are compared by means of a comparator, and a flip-flop is set in response to a comparison voltage of the comparator and reset in response to an external reset signal. The output of the flip-flop operates a transistor for controlling the discharge of a capacitor of the integrating circuit, and is taken out as an output pulse of the monostable multivibrator.
    Type: Grant
    Filed: October 26, 1978
    Date of Patent: August 12, 1980
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kazuhide Aoki, Kenji Kawagai, Akira Nagae, Shuichi Goto
  • Patent number: 4211942
    Abstract: A voltage comparator suitable for use in an analog-to-digital converter such as a successive-approximation converter, and provided with capacitively cascade-connected inverter stages to produce an output signal of a logic level 1 or 0 according to the relationship between the magnitudes of two analog input voltage signals to be compared. A first series circuit of an MOS switching transistor and resistive element is connected between the input and output of the respective inverters; a second series circuit of a MOS switching transistor and resistive element is connected between the input of each inverter and circuit ground. The MOS transistors of the first and second series circuits are simultaneously enabled or disabled by a clock pulse; and two input voltage signals to be compared are alternately applied to the first stage coupling capacitor.
    Type: Grant
    Filed: July 18, 1978
    Date of Patent: July 8, 1980
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kazuhide Aoki, Kenji Kawagai
  • Patent number: 4205263
    Abstract: There is provided a MOS field effect transistor circuit comprising a negative power terminal, an N-channel type field effect transistor with the substrate coupled to the negative power terminal, a diode coupled in the forward direction between the negative power terminal and the gate of the N-channel type field effect transistor, and a high-resistance resistor coupled between the junction of the diode and the gate of the N-channel type field effect transistor and an earth terminal. The variation in the threshold voltage of the N-channel type field effect transistor owing to temperature change is compensated by variation in the forward voltage of diode with the temperature change to keep constant the voltage applied to the gate of the field effect transistor, thereby securing the constant current property of the field effect transistor for temperature change.
    Type: Grant
    Filed: August 2, 1977
    Date of Patent: May 27, 1980
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Kenji Kawagai, Shigeki Yoshida
  • Patent number: 4173756
    Abstract: An abnormal voltage detection circuit includes a series circuit of a resistor and a capacitor coupled across a power source by means of a switch, an inverter with the input terminal coupled to the junction of the resistor and capacitor, and an R-S flip-flop circuit with the set and reset input terminals coupled to the output terminal of the inverter and a manual switch respectively. The R-S flip-flop circuit is set by a first threshold voltage lower than the threshold voltage of the inverter, and reset by a second threshold voltage higher than the threshold voltage of the inverter.
    Type: Grant
    Filed: December 7, 1977
    Date of Patent: November 6, 1979
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Kenji Kawagai, Shigeki Yoshida, Hisaharu Ogawa, Toshiro Ohashi
  • Patent number: 4151546
    Abstract: A semiconductor device comprising electrode-lead layer units wherein at least one of said electrode-lead layer units or at least one portion of same of said units occupying certain positions in the semiconductor device is made thicker than the remainder, thereby enabling circuit elements to be integrated with a high density, namely, rendering the entire semiconductor device compact.
    Type: Grant
    Filed: August 28, 1978
    Date of Patent: April 24, 1979
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Kenji Kawagai, Shigeki Yoshida, Yasuo Nakada
  • Patent number: 4129792
    Abstract: A driver circuit which comprises a driver stage; an inverter stage formed of an even number of mutually cascade connected inverters and connected to the output side of said driver stage; a first switching element rendered conducting or nonconducting according to a level of an output signal being received from said driver stage; and a second switching element rendered conducting or nonconducting according to a level of an output signal being received from said inverter stage.
    Type: Grant
    Filed: May 31, 1977
    Date of Patent: December 12, 1978
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Kenji Kawagai, Shigeki Yoshida
  • Patent number: 4122360
    Abstract: A logic circuit using CMOS transistors, in which electrical power is supplied to a CMOS logic circuit that is formed of P-channel type and N-channel type MOS transistors by way of a depletion type MOS transistor. The output level with respect to the voltage of the power source that is used is set at some point by the design of the depletion-type MOS transistor.
    Type: Grant
    Filed: July 29, 1977
    Date of Patent: October 24, 1978
    Assignee: Tokyo Shibaura Electric Company, Limited
    Inventors: Kenji Kawagai, Shigeki Yoshida