Abstract: A wireless communication apparatus includes a memory, and a processor coupled to the memory and configured to calculate a variation amount based on a frequency difference between a first clock signal in a first synchronous processing apparatus and a second clock signal in the wireless communication apparatus according to a first message exchanged between the first synchronous processing apparatus and the wireless communication apparatus, calculate a correction amount based on a phase difference between a first time in a second synchronous processing apparatus and a second time in the wireless communication apparatus according to a second message exchanged between the second synchronous processing apparatus and the wireless communication apparatus, and when a failure is detected in the first synchronous processing apparatus based on the variation amount and the correction amount, switch an object for synchronization from the first synchronous processing apparatus to the second synchronous processing apparatus.

Abstract: A communication apparatus, for relaying a time synchronizing signal between a master and a slave that transmit PTP (Precision Time Protocol) signals, stores a first time of the communication apparatus at a point in time that the communication apparatus receives a first time synchronizing signal addressed to the slave, obtains a second time of the master at a point in time that the first time synchronizing signal is transmitted from the master, from the first time synchronizing signal or the like, obtains an amount of offset that is a difference between a reference time of the master and a reference time of the communication apparatus, using the first time as a time of the slave and the second time as the time of the master in a time synchronizing algorithm of the PTP, and corrects the reference time of the communication apparatus using the amount of offset.

Abstract: A control device for a clock generation circuit that generates a clock signal based on a reference signal from an outside, the control device includes: a storage device that stores frequency correction information for the clock signal according to a temperature condition of the clock generation circuit; and a processor that controls a frequency of the clock signal generated by the clock generation circuit under a second temperature condition, based on first and second frequency correction information according to a first temperature condition at first and second time points in the storage device.

Abstract: A base station system includes a radio control device and a radio device, the radio control device transmits first time information and data to the radio device, the radio device includes an antenna and is configured to receive the first time information and the data generate second time information synchronized with the first time information based on the first time information, store the data into a buffer, identify, based on the second time information, a first timing when the data is to be transmitted from the antenna, identify, based on a difference between the first timing and a second timing specified based on a system clock recovered from the received data, a third timing when the data is to be read from the buffer, read the data stored in the buffer at the identified third timing, and control the antenna to transmit the data read from the buffer.

Abstract: A control device for a clock generation circuit that generates a clock signal based on a reference signal from an outside, the control device includes: a storage device that stores frequency correction information for the clock signal according to a temperature condition of the clock generation circuit; and a processor that controls a frequency of the clock signal generated by the clock generation circuit under a second temperature condition, based on first and second frequency correction information according to a first temperature condition at first and second time points in the storage device.

Abstract: A communication signal suppressing apparatus capable of reducing a load of a firmware using portion is provided in a communication signal apparatus such as a common line signal apparatus. A common line signal processing circuit corresponds to hardware used to execute a portion of the level-2 process operation, and this common line signal processing circuit owns such a function capable of discarding a reception frame having no meaning other than a confirmation response, and also capable of extracting a reverse-direction sequence number thereof. As a result, the common line signal processing circuit performs a remaining level-2 process operation. Thus, since a workload of a processing apparatus (CPU) using the firmware can be reduced, this firmware can be designed with sufficient capacities. Also, other process operations can be carried out by this CPU.