Abstract: An image forming apparatus includes a housing in which an image forming unit is to be mounted, a support that supports an image reading device in a state where the image reading device is separated from the housing, and a guiding portion in which a guide part, which is formed on a to-be-mounted surface of an add-on device in such a manner as to project, is to be inserted such that the guide part is guided by the guiding portion. Engagement holes with which engagement portions, which are formed on the to-be-mounted surface of the add-on device in such a manner as to project, are to be engaged such that the engagement portions are positioned by the engagement holes are formed in a mounting surface of the housing on which the add-on device is to be mounted.

Abstract: An image forming apparatus includes a housing in which an image forming unit is to be mounted, a support that supports an image reading device in a state where the image reading device is separated from the housing, and a guiding portion in which a guide part, which is formed on a to-be-mounted surface of an add-on device in such a manner as to project, is to be inserted such that the guide part is guided by the guiding portion. Engagement holes with which engagement portions, which are formed on the to-be-mounted surface of the add-on device in such a manner as to project, are to be engaged such that the engagement portions are positioned by the engagement holes are formed in a mounting surface of the housing on which the add-on device is to be mounted.

Abstract: A device includes a III-N layer having an upper side and a lower side, the lower side being opposite the upper side, and at least one conductive contact on the upper side of the III-N layer, the conductive contact extending into the III-N layer. The conductive contact comprises a top side facing away from the lower side of the III-N layer, and a bottom side facing towards the lower side of the III-N layer. The bottom side includes a first end and a second end opposite the first end, a first side rising from the first end to an intermediate point closer to the top side than the first end, and a second side falling from the intermediate point to the second end further from the top side than the intermediate point.

Abstract: A device includes a III-N layer having an upper side and a lower side, the lower side being opposite the upper side, and at least one conductive contact on the upper side of the III-N layer, the conductive contact extending into the III-N layer. The conductive contact comprises a top side facing away from the lower side of the III-N layer, and a bottom side facing towards the lower side of the III-N layer. The bottom side includes a first end and a second end opposite the first end, a first side rising from the first end to an intermediate point closer to the top side than the first end, and a second side falling from the intermediate point to the second end further from the top side than the intermediate point.

Abstract: An AlGaN/GaN HEMT includes: a compound semiconductor layer; a source electrode and a drain electrode formed on an upper side of the compound semiconductor layer; and an Al—Si—N layer being a high-resistance layer disposed in a lower portion of at least one of the source electrode and the drain electrode and higher in an electric resistance value than the source electrode and the drain electrode.

Abstract: An AlGaN/GaN HEMT includes: a compound semiconductor layer; a source electrode and a drain electrode formed on an upper side of the compound semiconductor layer; and an Al—Si—N layer being a high-resistance layer disposed in a lower portion of at least one of the source electrode and the drain electrode and higher in an electric resistance value than the source electrode and the drain electrode.

Abstract: An AlGaN/GaN HEMT includes: a compound semiconductor layer; a source electrode and a drain electrode formed on an upper side of the compound semiconductor layer; and an Al—Si—N layer being a high-resistance layer disposed in a lower portion of at least one of the source electrode and the drain electrode and higher in an electric resistance value than the source electrode and the drain electrode.

Abstract: An AlGaN/GaN HEMT includes: a compound semiconductor layer; a source electrode and a drain electrode formed on an upper side of the compound semiconductor layer; and an Al—Si—N layer being a high-resistance layer disposed in a lower portion of at least one of the source electrode and the drain electrode and higher in an electric resistance value than the source electrode and the drain electrode.

Abstract: Provided is a disk device, including: a disk mounting portion; a pickup slider; a shaft configured to move the pickup slider; a conductive wire that contacts or is arranged in the vicinity of at least the shaft; and a ground component arranged such that the ground component contacts the conductive wire.

Abstract: A semiconductor device manufacturing method, includes a step of forming a first alumina film (underlying insulating film) 37 on a semiconductor substrate 20, a step of forming a first conductive film 41, a ferroelectric film 42, and a second conductive film 43 in sequence on the first alumina film 37, a step of forming a mask material film 45 on the second conductive film 43, a step of shaping the mask material film 45 into an auxiliary mask 45a, a step of shaping the second conductive film 43 into an upper electrode 43a by an etching using the auxiliary mask 45a and a first resist pattern 46 as a mask, a step of shaping the ferroelectric film 42 into a capacitor dielectric film 42a by patterning, and a step of shaping the first conductive film 41 into a lower electrode 41a by patterning, whereby a capacitor Q is constructed by the lower electrode 41, the capacitor dielectric film 42a, and the upper electrode 43a.

Abstract: A semiconductor device manufacturing method whereby a capacitor protective layer for ferroelectric capacitors of FeRAM can be prevented from peeling off. A lower electrode layer, a ferroelectric layer and an upper electrode layer are successively formed one upon another. The upper electrode layer is etched to form an upper electrode pattern, then the ferroelectric layer is etched to form a ferroelectric pattern, and a chemical solution treatment is performed on the resulting structure by using a mixed liquid of ammonia, hydrogen peroxide and water. Subsequently, a capacitor protective layer is formed, and then the lower electrode layer is etched to form a lower electrode pattern. A volatile etching residue produced during the formation of the ferroelectric pattern and adhering to the wafer surface, including the exposed lower electrode layer, is removed by the chemical solution treatment, whereby the subsequently formed capacitor protective layer is prevented from peeling off.

Abstract: A method for fabricating a semiconductor device that prevents an etching residue left at the time of making a contact hole which connects with a ferroelectric capacitor from adhering to the surface of a wafer. In order to make a contact hole which connects with an upper electrode or a lower electrode of the ferroelectric capacitor, a resist mask with predetermined thickness is formed and etching is performed so as to make the shape of the resist mask around an opening after the making of the contact hole taper as a result of widening the diameter of the opening and to make the thickness of a vertical portion of the resist mask around the opening approximately zero. Therefore, even if an etching residue left as a result of, for example, the over-etching of an electrode material adheres to the sidewall of the opening in the resist mask having a taper shape, the etching residue is removed by the etching. As a result, the possibility that the etching residue remains after the etching is small.

Abstract: A semiconductor device manufacturing method includes a step of forming an oxidation preventing film 25 on a contact plug 22a on a silicon substrate 10, a step of forming a capacitor Q on the oxidation preventing film 25, a step of forming a second interlayer insulating film 44 to cover the capacitor Q, a step of forming a first hole 44a in the second interlayer insulating film 44, a step of applying a brush scrubbing process to the second interlayer insulating film 44, a step of applying a wet process to the second interlayer insulating film 44, a step of forming a second hole 44c in the second interlayer insulating film 44 by using the oxidation preventing film 25 as a stopper, a step of etching the oxidation preventing film 25 under the second hole 44c to remove and also cleaning an upper electrode 33a under the first hole 44a, and a step of forming first and second conductive plugs 50a, 50c in the first and second holes 44a, 44c.

Abstract: A semiconductor device manufacturing method, includes a step of forming a first alumina film (underlying insulating film) 37 on a semiconductor substrate 20, a step of forming a first conductive film 41, a ferroelectric film 42, and a second conductive film 43 in sequence on the first alumina film 37, a step of forming a mask material film 45 on the second conductive film 43, a step of shaping the mask material film 45 into an auxiliary mask 45a, a step of shaping the second conductive film 43 into an upper electrode 43a by an etching using the auxiliary mask 45a and a first resist pattern 46 as a mask, a step of shaping the ferroelectric film 42 into a capacitor dielectric film 42a by patterning, and a step of shaping the first conductive film 41 into a lower electrode 41a by patterning, whereby a capacitor Q is constructed by the lower electrode 41, the capacitor dielectric film 42a, and the upper electrode 43a.