Abstract: A mask ROM device includes a plurality of memory cells each having an enhancement type FET having a gate electrode and first and second source/drain regions, a plurality of word lines connected to the gate electrodes, a plurality of bit lines connected to the first source/drain regions, a connection line formed above the gate electrode so as to electrically connect the first and second source/drain regions through contact holes in each of memory cells selected according to information to be stored.

Abstract: A read only semiconductor memory device includes a plurality of address coincidence detecting circuits, each of which has a specific address region assigned thereto and generates an address coincidence detecting signal when an input address signal designates an address in the assigned region. A priority circuit determines a priority order among the plurality of address coincidence detection signals from the plurality of coincidence detecting circuits. In accordance with a signal to which priority is given by the priority circuit, a data output terminal receives memory cell data read from a memory array or is fixed at a predetermined logical level. With respect to a memory address region containing a succession of only data of logic "1" or "0" (that is, a region with all "1's" or "0's"), data of a logical level predetermined by a switching circuit is output to the data output terminal. For this memory address region, fixed data, which is not read from the memory array, is outputted.

Abstract: A memory cell array is divided into a plurality of subregions along row and column directions. In data reading, 1-bit memory cell is selected from each of the subregions which are arranged on different rows and different columns in this memory cell array. Data are simultaneously read from the simultaneously selected memory cells. The simultaneously read data include information bits and at least one error checking bit. Only data of a 1-bit memory cell is read from one word line at the maximum. Thus, it is possible to extremely reduce a probability that two or more erroneous data bits are included in a plurality of bits of simultaneously read data even if a selected word line is defective. It is possible to execute error checking and correction in accordance with an ECC scheme, improving repairability for defective bits in a semiconductor memory device.

Abstract: A mask ROM having an ECC for error correction by carrying out operation according to a Hamming matrix in which all but 2 of 6 elements in one column and the other column match each other. The columns correspond to 32 data that will be provided to an external source, and the one column corresponds to the other column by 16 columns. The ECC is implemented so that one half of 32 correction signals with which exclusive ORs are to be taken with 32 data, are generated by a circuit identical to that of a circuit for generating the other half of the 32 correction signals; and the circuit for taking the exclusive ORs from one half of the 32 data and the corresponding correction signals can be used for taking exclusive ORs from the remaining half of the 32 data and the corresponding correction signals.

Abstract: A sense amplifier for nonvolatile semiconductor storage devices, wherein a first reference voltage is generated from a first reference voltage generating circuit and a second reference voltage is generated from a second reference voltage generating circuit. A latch type sense amplifier is provided, which is connected to a bit line via a selection transistor. The latch type sense amplifier includes input/output terminals in two directions and serves to latch information when the input voltage at one input/output terminal is higher than the voltage at the other input/output terminal. A first gate transistor, conductive in response to the second reference voltage, is connected between the output of the first reference voltage generating circuit and the one input/output terminal for the latch type sense amplifier. A second gate transistor, conductive in response to the second reference voltage, is connected between a load and the other input/output terminal of the latch type sense amplifier.

Abstract: In a nonvolatile semiconductor device in which source metal interconnections for coupling to ground a source of a floating gate type memory transistor are commonly provided for each predetermined plurality of memory transistors, switching transistors are provided for each column for coupling to ground columns excluding the selected column when a single column is selected in response to an external column address. Each of the switching transistors operates in response to an inverted signal of an output of a column decoder. According to this structure, a variation in source potential of each memory transistor caused by the difference in source resistance associated with each of the memory transistors is reduced.

Abstract: An EPROM as a nonvolatile semiconductor memory device includes a semiconductor substrate 1, a gate oxide layer 3 formed on the surface of the semiconductor substrate 1, a plurality of floating gates 4a and 4b formed on the gate oxide layer 3 so as to overlap one another at the portions 4ab thereof with a gate oxide layer 14 sandwiched between the overlapping portions 4ab, and control gate strips 5 formed on a gate oxide layer 6 which overlies the floating gates 4a and 4b.

Abstract: In a nonvolatile semiconductor device in which source metal interconnections for coupling to ground a source of a floating gate type memory transistor are commonly provided for each predetermined plurality of memory transistors, switching transistors are provided for each column for coupling to ground columns excluding the selected column when a single column is selected in response to an external column address. Each of the switching transistors operates in response to an inverted signal of an output of a column decoder. According to this structure, a variation in source potential of each memory transistor caused by the difference in source resistance associated with each of the memory transistors is reduced.

Abstract: In an output buffer circuit, two P channel MOSFET's (1, 2) are connected in parallel between a power supply terminal (16) and an output terminal (10), and two N channel MOSFET's (3, 4) are connected in parallel between the ground terminal (17) and the output terminal (10). When a normal power supply potential is applied to the power supply terminal (16), either one of the P channel MOSFET's (1, 2) or either one of N channel MOSFET's (3, 4) is turned on in response to an input signal. When a high potential is applied to the power supply terminal (16), two P channel MOSFET's (1, 2) or two N channel MOSFET's (3, 4) are turned on in response to the input signal.

Abstract: A memory cell array (100) of an EPROM includes a first data memory region (1a), a second data memory region (1b), a 2M code memory line (2a) and a 1M code memory line (2b). When both the first and the second data memory regions (1a, 1b) are normal, the EPROM may be used as a 2M bit EPROM, in which case a device code indicating that the EPROM is a 2M bit EPROM is read out from the 2M code memory line (2a). When a defective portion is present in one of the first and the second data memory regions (1a, 1b), the EPROM may be used as a 1M bit EPROM, in which case a device code indicating that the EPROM is a 1M bit EPROM is read out from the 1M code memory line (2b).

Abstract: A non-volatile memory cell includes a MOS transistor of double gate construction. The MOS memory transistor includes a floating gate structure which includes electrically separated first and second segmented floating gates (4a; 4b). For the purpose of writing data, electrons are independently injected into the first and second segmented floating gates. Data are stored in the MOS memory transistor in three different non-volatile storage levels; one with electron accumulated either one of the two segmented floating gates; another with electrons injected into both of the segmented floating gates; and still another with no electrons accumulated on both of the segmented floating gates.

Abstract: In an output buffer circuit, two P channel MOSFET's (1, 2) are connected in parallel between a power supply terminal (16) and an output terminal (10), and two N channel MOSFET's (3, 4) are connected in parallel between the ground terminal (17) and the output terminal (10). When a high potential is applied to the power supply terminal (16), either one of the P channel MOSFET's (1, 2) or either one of N channel MOSFET's (3, 4) is turned on in response to an input signal. When a normal power supply potential is applied to the power supply terminal (16), two P channel MOSFET's (1, 2) or two N channel MOSFET's (3, 4) are turned on in response to the input signal.

Abstract: An EEPROM having an ECC circuit further comprises a counter circuit. The ECC circuit checks and corrects bit errors included in data read out from a memory cell array. In addition, the ECC circuit generates a predetermined signal every time it corrects a bit error. The counter circuit counts a predetermined signal generated from the ECC circuit.

Abstract: Memory transistors are arranged in a plurality of rows and a plurality of columns. A source line is formed for every two bit lines formed in the column direction, each connected to the memory transistors of one column. A source region of each memory transistor is connected, on one side, to a source line adjacent thereto and, on the other side, to a source line through the source region of the adjacent memory transistor, through impurity regions respectively. A floating gate is formed to extend to a position under the corresponding source line. In another example, a source line is formed for each bit line formed in the column direction. The source region of each memory transistor is connected to the adjacent source lines on both sides thereof through impurity regions. The floating gate is formed to extend to positions under both adjacent source lines.

Abstract: A semiconductor memory device comprises a main memory 101 and a spare memory 102. When a part of the memory cells of the main memory 101 are defective, these defective memory cells are replaced by memory cells in the spare memory 102. The space memory 102 is decoded by the decoder circuit 104. The decoder circuit 104 is capable of decoding the spare memory 102 using a signal of an instruction memory 107. The instruction memory 107 is selectively enabled or disabled by an instruction control circuit 108. Consequently, in a state in which the instruction memory 107 is disabled by the control circuit 108, a spare memory selection signal is not provided from the instruction memory 107 to the decoder circuit 104 and the semiconductor memory device normally decodes the main memory including defective memory cells. As a result, the addresses and the like of the defective memory cells can be determined.

Abstract: A variable-threshold non-volatile memory in which a potential falling between a selection and a non-selection level is applied to the gates and the resultant drain current is measured to determine if one of the transistors has an abnormal threshold voltage.