Patents by Inventor Kenji Komeda
Kenji Komeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10354803Abstract: A device includes a capacitor that has first and second electrodes having a capacitor insulator there-between. The first electrode is elongated and extends elevationally. The first electrode has elevationally-extending first conductive material and has second conductive material that projects laterally outward from an elevationally-extending part of the first conductive material. The laterally-projecting second conductive material has a vertical thickness that is less than that of the elevationally-extending first conductive material. Support material laterally supports the capacitor and contacts a tip end of the laterally-projecting second conductive material.Type: GrantFiled: January 15, 2019Date of Patent: July 16, 2019Assignee: Micron Technology, Inc.Inventors: Kenji Komeda, Kana Suzuki
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Publication number: 20190148078Abstract: A device includes a capacitor that has first and second electrodes having a capacitor insulator there-between. The first electrode is elongated and extends elevationally. The first electrode has elevationally-extending first conductive material and has second conductive material that projects laterally outward from an elevationally-extending part of the first conductive material. The laterally-projecting second conductive material has a vertical thickness that is less than that of the elevationally-extending first conductive material. Support material laterally supports the capacitor and contacts a tip end of the laterally-projecting second conductive material.Type: ApplicationFiled: January 15, 2019Publication date: May 16, 2019Applicant: Micron Technology, Inc.Inventors: Kenji Komeda, Kana Suzuki
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Patent number: 10217569Abstract: A device includes a capacitor that has first and second electrodes having a capacitor insulator there-between. The first electrode is elongated and extends elevationally. The first electrode has elevationally-extending first conductive material and has second conductive material that projects laterally outward from an elevationally-extending part of the first conductive material. The laterally-projecting second conductive material has a vertical thickness that is less than that of the elevationally-extending first conductive material. Support material laterally supports the capacitor and contacts a tip end of the laterally-projecting second conductive material.Type: GrantFiled: October 18, 2016Date of Patent: February 26, 2019Assignee: Micron Technology, Inc.Inventors: Kenji Komeda, Kana Suzuki
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Patent number: 9997592Abstract: A capacitor includes an elevationally inner capacitor electrode, an elevationally outer capacitor electrode, and capacitor insulator between the elevationally inner and outer capacitor electrodes. The elevationally inner capacitor electrode comprises a hollow longitudinally-elongated conductive cylinder-like portion and a non-hollow longitudinally-elongated conductive cylinder-like portion electrically coupled with the hollow cylinder-like portion. The non-hollow cylinder-like portion is radially of and extends longitudinally along a longitudinal side surface of the hollow cylinder-like portion. Additional embodiments and aspects are disclosed.Type: GrantFiled: December 1, 2015Date of Patent: June 12, 2018Assignee: Micron Technology, Inc.Inventor: Kenji Komeda
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Publication number: 20180108486Abstract: A device comprises a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is elongated and extends elevationally. The first electrode comprises elevationally-extending first conductive material and comprises second conductive material that projects laterally outward from an elevationally-extending part of the first conductive material. The laterally-projecting second conductive material has a vertical thickness that is less than that of the elevationally-extending first conductive material. Support material laterally supports the capacitor and contacts a tip end of the laterally-projecting second conductive material.Type: ApplicationFiled: October 18, 2016Publication date: April 19, 2018Inventors: Kenji KOMEDA, Kana Suzuki
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Publication number: 20170154952Abstract: A capacitor includes an elevationally inner capacitor electrode, an elevationally outer capacitor electrode, and capacitor insulator between the elevationally inner and outer capacitor electrodes. The elevationally inner capacitor electrode comprises a hollow longitudinally-elongated conductive cylinder-like portion and a non-hollow longitudinally-elongated conductive cylinder-like portion electrically coupled with the hollow cylinder-like portion. The non-hollow cylinder-like portion is radially of and extends longitudinally along a longitudinal side surface of the hollow cylinder-like portion. Additional embodiments and aspects are disclosed.Type: ApplicationFiled: December 1, 2015Publication date: June 1, 2017Inventor: Kenji KOMEDA
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Patent number: 9431403Abstract: A semiconductor device provided with a capacitor that includes a plurality of cylindrical or columnar storage electrodes provided periodically on a semiconductor substrate, capacitor insulation films that cover the wall surfaces of the storage electrodes, and first conductive films provided on the capacitor insulation film and facing the storage electrodes, wherein the first conductive films of the capacitors adjacent in a first direction in which the storage electrodes are arranged are in contact with each other, and the first conductive films of capacitors adjacent in remaining other directions in which the storage electrodes are arranged are separated from each other.Type: GrantFiled: October 2, 2013Date of Patent: August 30, 2016Assignee: PS4 Luxco S.a.r.l.Inventor: Kenji Komeda
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Publication number: 20150279842Abstract: A semiconductor device provided with a capacitor that includes a plurality of cylindrical or columnar storage electrodes provided periodically on a semiconductor substrate, capacitor insulation films that cover the wall surfaces of the storage electrodes, and first conductive films provided on the capacitor insulation film and facing the storage electrodes, wherein the first conductive films of the capacitors adjacent in a first direction in which the storage electrodes are arranged are in contact with each other, and the first conductive films of capacitors adjacent in remaining other directions in which the storage electrodes are arranged are separated from each other.Type: ApplicationFiled: October 2, 2013Publication date: October 1, 2015Inventor: Kenji Komeda
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Patent number: 8586430Abstract: In a method of manufacturing a capacitor, a lower electrode of a capacitor is formed on or above a semiconductor substrate. An ozone gas and an inert gas are simultaneously introduced for a predetermined period into a reaction chamber of an atomic layer deposition apparatus in which the semiconductor substrate is set. Then, the ozone gas is exhausted from the reaction chamber by stopping the introduction of the ozone gas and introducing only the inert gas into the reaction chamber, after the introduction. A capacitive dielectric film is formed on the lower electrode by an atomic layer deposition (ALD) method in the atom layer deposition apparatus. An upper electrode of the capacitor is formed on the capacitive dielectric film after the capacitive dielectric film is formed.Type: GrantFiled: January 24, 2007Date of Patent: November 19, 2013Assignee: Elpida Memory, Inc.Inventor: Kenji Komeda
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Patent number: 8188529Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.Type: GrantFiled: January 7, 2009Date of Patent: May 29, 2012Assignee: Elpida Memory, Inc.Inventors: Yoshitaka Nakamura, Kenji Komeda, Ryota Suewaka, Noriaki Ikeda
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Patent number: 8124493Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first insulating film is formed over a substrate. A second insulating film is formed on the first insulating film. An electrode penetrating the first and the second insulating films is formed. A part of the second insulating film and a part of the electrode are removed so that a first hole is formed in the second insulating film. A first portion of the electrode is exposed through the first hole. A part of the first portion of the electrode is removed by an isotropic etching.Type: GrantFiled: July 29, 2010Date of Patent: February 28, 2012Assignee: Elpida Memory, Inc.Inventor: Kenji Komeda
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Publication number: 20110027963Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first insulating film is formed over a substrate. A second insulating film is formed on the first insulating film. An electrode penetrating the first and the second insulating films is formed. A part of the second insulating film and a part of the electrode are removed so that a first hole is formed in the second insulating film. A first portion of the electrode is exposed through the first hole. A part of the first portion of the electrode is removed by an isotropic etching.Type: ApplicationFiled: July 29, 2010Publication date: February 3, 2011Inventor: Kenji Komeda
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Patent number: 7763500Abstract: First, a base structure provided with the main parts of a memory cell is prepared, and a lower electrode comprising a polycrystalline silicon film is thereafter formed on the base structure. Next, the surface of the lower electrode is thermally nitrided at a predetermined temperature to form a silicon nitride film. In the thermal nitridation of the lower electrode, the temperature is increased to a predetermined nitriding temperature, after which the temperature is reduced at a rate that is more gradual than usual. Aluminum oxide (Al2O3) or another metal oxide dielectric film is thereafter formed as the capacitive insulating film on the lower electrode, and an upper electrode is formed on the capacitive insulating film.Type: GrantFiled: August 3, 2006Date of Patent: July 27, 2010Assignee: Elpida Memory, Inc.Inventors: Takashi Arao, Kenichi Koyanagi, Kenji Komeda, Naruhiko Nakanishi, Hideki Gomi
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Publication number: 20090263968Abstract: A method of fabricating a semiconductor device includes: forming a conductive film over a semiconductor wafer; forming a mask film over the conductive film; removing a portion of the mask film covering at least a peripheral portion of the semiconductor wafer such that a portion of the mask film covering a device forming region of the semiconductor wafer remains; and removing an exposed portion of the conductive film with use of the remaining portion of the mask film as a mask.Type: ApplicationFiled: April 10, 2009Publication date: October 22, 2009Applicant: ELPIDA MEMORY, INC.Inventor: Kenji Komeda
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Publication number: 20090179246Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.Type: ApplicationFiled: January 7, 2009Publication date: July 16, 2009Inventors: Yoshitaka NAKAMURA, Kenji KOMEDA, Ryota SUEWAKA, Noriaki IKEDA
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Publication number: 20080176412Abstract: An atomic layer deposition system includes a reaction chamber, a plurality of exhaust tubes communicated to the reaction chamber, a plurality of first vacuum gauges for monitoring the degree of vacuum of the respective exhaust tubes, a second vacuum gauge for monitoring the degree of vacuum of the reaction chamber, and control valves for adjusting the exhaust volume of the exhaust tubes independently of one another. The control valves are controlled based on the pressures measured by the first and second control valves for achieving a uniform flow of the vapor phase reactant.Type: ApplicationFiled: January 22, 2008Publication date: July 24, 2008Applicant: ELPIDA MEMORY, INC.Inventor: Kenji Komeda
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Publication number: 20070173028Abstract: In a method of manufacturing a capacitor, a lower electrode of a capacitor is formed on or above a semiconductor substrate. An ozone gas and an inert gas are simultaneously introduced for a predetermined period into a reaction chamber of an atomic layer deposition apparatus in which the semiconductor substrate is set. Then, the ozone gas is exhausted from the reaction chamber by stopping the introduction of the ozone gas and introducing only the inert gas into the reaction chamber, after the introduction. A capacitive dielectric film is formed on the lower electrode by an atomic layer deposition (ALD) method in the atom layer deposition apparatus. An upper electrode of the capacitor is formed on the capacitive dielectric film after the capacitive dielectric film is formed.Type: ApplicationFiled: January 24, 2007Publication date: July 26, 2007Applicant: ELPIDA MEMORY, INC.Inventor: Kenji Komeda
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Publication number: 20070032034Abstract: First, a base structure provided with the main parts of a memory cell is prepared, and a lower electrode comprising a polycrystalline silicon film is thereafter formed on the base structure. Next, the surface of the lower electrode is thermally nitrided at a predetermined temperature to form a silicon nitride film. In the thermal nitridation of the lower electrode, the temperature is increased to a predetermined nitriding temperature, after which the temperature is reduced at a rate that is more gradual than usual. Aluminum oxide (Al2O3) or another metal oxide dielectric film is thereafter formed as the capacitive insulating film on the lower electrode, and an upper electrode is formed on the capacitive insulating film.Type: ApplicationFiled: August 3, 2006Publication date: February 8, 2007Inventors: Takashi Arao, Kenichi Koyanagi, Kenji Komeda, Naruhiko Nakanishi, Hideki Gomi
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Patent number: RE46882Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.Type: GrantFiled: November 12, 2014Date of Patent: May 29, 2018Assignee: Longitude Semiconductor S.a.r.l.Inventors: Yoshitaka Nakamura, Kenji Komeda, Ryota Suewaka, Noriaki Ikeda
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Patent number: RE47988Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.Type: GrantFiled: May 28, 2018Date of Patent: May 12, 2020Assignee: Longitude Licensing LimitedInventors: Yoshitaka Nakamura, Kenji Komeda, Ryota Suewaka, Noriaki Ikeda