Patents by Inventor Kenji Komeda

Kenji Komeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10354803
    Abstract: A device includes a capacitor that has first and second electrodes having a capacitor insulator there-between. The first electrode is elongated and extends elevationally. The first electrode has elevationally-extending first conductive material and has second conductive material that projects laterally outward from an elevationally-extending part of the first conductive material. The laterally-projecting second conductive material has a vertical thickness that is less than that of the elevationally-extending first conductive material. Support material laterally supports the capacitor and contacts a tip end of the laterally-projecting second conductive material.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kenji Komeda, Kana Suzuki
  • Publication number: 20190148078
    Abstract: A device includes a capacitor that has first and second electrodes having a capacitor insulator there-between. The first electrode is elongated and extends elevationally. The first electrode has elevationally-extending first conductive material and has second conductive material that projects laterally outward from an elevationally-extending part of the first conductive material. The laterally-projecting second conductive material has a vertical thickness that is less than that of the elevationally-extending first conductive material. Support material laterally supports the capacitor and contacts a tip end of the laterally-projecting second conductive material.
    Type: Application
    Filed: January 15, 2019
    Publication date: May 16, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Kenji Komeda, Kana Suzuki
  • Patent number: 10217569
    Abstract: A device includes a capacitor that has first and second electrodes having a capacitor insulator there-between. The first electrode is elongated and extends elevationally. The first electrode has elevationally-extending first conductive material and has second conductive material that projects laterally outward from an elevationally-extending part of the first conductive material. The laterally-projecting second conductive material has a vertical thickness that is less than that of the elevationally-extending first conductive material. Support material laterally supports the capacitor and contacts a tip end of the laterally-projecting second conductive material.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: February 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kenji Komeda, Kana Suzuki
  • Patent number: 9997592
    Abstract: A capacitor includes an elevationally inner capacitor electrode, an elevationally outer capacitor electrode, and capacitor insulator between the elevationally inner and outer capacitor electrodes. The elevationally inner capacitor electrode comprises a hollow longitudinally-elongated conductive cylinder-like portion and a non-hollow longitudinally-elongated conductive cylinder-like portion electrically coupled with the hollow cylinder-like portion. The non-hollow cylinder-like portion is radially of and extends longitudinally along a longitudinal side surface of the hollow cylinder-like portion. Additional embodiments and aspects are disclosed.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: June 12, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kenji Komeda
  • Publication number: 20180108486
    Abstract: A device comprises a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is elongated and extends elevationally. The first electrode comprises elevationally-extending first conductive material and comprises second conductive material that projects laterally outward from an elevationally-extending part of the first conductive material. The laterally-projecting second conductive material has a vertical thickness that is less than that of the elevationally-extending first conductive material. Support material laterally supports the capacitor and contacts a tip end of the laterally-projecting second conductive material.
    Type: Application
    Filed: October 18, 2016
    Publication date: April 19, 2018
    Inventors: Kenji KOMEDA, Kana Suzuki
  • Publication number: 20170154952
    Abstract: A capacitor includes an elevationally inner capacitor electrode, an elevationally outer capacitor electrode, and capacitor insulator between the elevationally inner and outer capacitor electrodes. The elevationally inner capacitor electrode comprises a hollow longitudinally-elongated conductive cylinder-like portion and a non-hollow longitudinally-elongated conductive cylinder-like portion electrically coupled with the hollow cylinder-like portion. The non-hollow cylinder-like portion is radially of and extends longitudinally along a longitudinal side surface of the hollow cylinder-like portion. Additional embodiments and aspects are disclosed.
    Type: Application
    Filed: December 1, 2015
    Publication date: June 1, 2017
    Inventor: Kenji KOMEDA
  • Patent number: 9431403
    Abstract: A semiconductor device provided with a capacitor that includes a plurality of cylindrical or columnar storage electrodes provided periodically on a semiconductor substrate, capacitor insulation films that cover the wall surfaces of the storage electrodes, and first conductive films provided on the capacitor insulation film and facing the storage electrodes, wherein the first conductive films of the capacitors adjacent in a first direction in which the storage electrodes are arranged are in contact with each other, and the first conductive films of capacitors adjacent in remaining other directions in which the storage electrodes are arranged are separated from each other.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: August 30, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Kenji Komeda
  • Publication number: 20150279842
    Abstract: A semiconductor device provided with a capacitor that includes a plurality of cylindrical or columnar storage electrodes provided periodically on a semiconductor substrate, capacitor insulation films that cover the wall surfaces of the storage electrodes, and first conductive films provided on the capacitor insulation film and facing the storage electrodes, wherein the first conductive films of the capacitors adjacent in a first direction in which the storage electrodes are arranged are in contact with each other, and the first conductive films of capacitors adjacent in remaining other directions in which the storage electrodes are arranged are separated from each other.
    Type: Application
    Filed: October 2, 2013
    Publication date: October 1, 2015
    Inventor: Kenji Komeda
  • Patent number: 8586430
    Abstract: In a method of manufacturing a capacitor, a lower electrode of a capacitor is formed on or above a semiconductor substrate. An ozone gas and an inert gas are simultaneously introduced for a predetermined period into a reaction chamber of an atomic layer deposition apparatus in which the semiconductor substrate is set. Then, the ozone gas is exhausted from the reaction chamber by stopping the introduction of the ozone gas and introducing only the inert gas into the reaction chamber, after the introduction. A capacitive dielectric film is formed on the lower electrode by an atomic layer deposition (ALD) method in the atom layer deposition apparatus. An upper electrode of the capacitor is formed on the capacitive dielectric film after the capacitive dielectric film is formed.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: November 19, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Kenji Komeda
  • Patent number: 8188529
    Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: May 29, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Yoshitaka Nakamura, Kenji Komeda, Ryota Suewaka, Noriaki Ikeda
  • Patent number: 8124493
    Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first insulating film is formed over a substrate. A second insulating film is formed on the first insulating film. An electrode penetrating the first and the second insulating films is formed. A part of the second insulating film and a part of the electrode are removed so that a first hole is formed in the second insulating film. A first portion of the electrode is exposed through the first hole. A part of the first portion of the electrode is removed by an isotropic etching.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: February 28, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Kenji Komeda
  • Publication number: 20110027963
    Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first insulating film is formed over a substrate. A second insulating film is formed on the first insulating film. An electrode penetrating the first and the second insulating films is formed. A part of the second insulating film and a part of the electrode are removed so that a first hole is formed in the second insulating film. A first portion of the electrode is exposed through the first hole. A part of the first portion of the electrode is removed by an isotropic etching.
    Type: Application
    Filed: July 29, 2010
    Publication date: February 3, 2011
    Inventor: Kenji Komeda
  • Patent number: 7763500
    Abstract: First, a base structure provided with the main parts of a memory cell is prepared, and a lower electrode comprising a polycrystalline silicon film is thereafter formed on the base structure. Next, the surface of the lower electrode is thermally nitrided at a predetermined temperature to form a silicon nitride film. In the thermal nitridation of the lower electrode, the temperature is increased to a predetermined nitriding temperature, after which the temperature is reduced at a rate that is more gradual than usual. Aluminum oxide (Al2O3) or another metal oxide dielectric film is thereafter formed as the capacitive insulating film on the lower electrode, and an upper electrode is formed on the capacitive insulating film.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: July 27, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Takashi Arao, Kenichi Koyanagi, Kenji Komeda, Naruhiko Nakanishi, Hideki Gomi
  • Publication number: 20090263968
    Abstract: A method of fabricating a semiconductor device includes: forming a conductive film over a semiconductor wafer; forming a mask film over the conductive film; removing a portion of the mask film covering at least a peripheral portion of the semiconductor wafer such that a portion of the mask film covering a device forming region of the semiconductor wafer remains; and removing an exposed portion of the conductive film with use of the remaining portion of the mask film as a mask.
    Type: Application
    Filed: April 10, 2009
    Publication date: October 22, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Kenji Komeda
  • Publication number: 20090179246
    Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.
    Type: Application
    Filed: January 7, 2009
    Publication date: July 16, 2009
    Inventors: Yoshitaka NAKAMURA, Kenji KOMEDA, Ryota SUEWAKA, Noriaki IKEDA
  • Publication number: 20080176412
    Abstract: An atomic layer deposition system includes a reaction chamber, a plurality of exhaust tubes communicated to the reaction chamber, a plurality of first vacuum gauges for monitoring the degree of vacuum of the respective exhaust tubes, a second vacuum gauge for monitoring the degree of vacuum of the reaction chamber, and control valves for adjusting the exhaust volume of the exhaust tubes independently of one another. The control valves are controlled based on the pressures measured by the first and second control valves for achieving a uniform flow of the vapor phase reactant.
    Type: Application
    Filed: January 22, 2008
    Publication date: July 24, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Kenji Komeda
  • Publication number: 20070173028
    Abstract: In a method of manufacturing a capacitor, a lower electrode of a capacitor is formed on or above a semiconductor substrate. An ozone gas and an inert gas are simultaneously introduced for a predetermined period into a reaction chamber of an atomic layer deposition apparatus in which the semiconductor substrate is set. Then, the ozone gas is exhausted from the reaction chamber by stopping the introduction of the ozone gas and introducing only the inert gas into the reaction chamber, after the introduction. A capacitive dielectric film is formed on the lower electrode by an atomic layer deposition (ALD) method in the atom layer deposition apparatus. An upper electrode of the capacitor is formed on the capacitive dielectric film after the capacitive dielectric film is formed.
    Type: Application
    Filed: January 24, 2007
    Publication date: July 26, 2007
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Kenji Komeda
  • Publication number: 20070032034
    Abstract: First, a base structure provided with the main parts of a memory cell is prepared, and a lower electrode comprising a polycrystalline silicon film is thereafter formed on the base structure. Next, the surface of the lower electrode is thermally nitrided at a predetermined temperature to form a silicon nitride film. In the thermal nitridation of the lower electrode, the temperature is increased to a predetermined nitriding temperature, after which the temperature is reduced at a rate that is more gradual than usual. Aluminum oxide (Al2O3) or another metal oxide dielectric film is thereafter formed as the capacitive insulating film on the lower electrode, and an upper electrode is formed on the capacitive insulating film.
    Type: Application
    Filed: August 3, 2006
    Publication date: February 8, 2007
    Inventors: Takashi Arao, Kenichi Koyanagi, Kenji Komeda, Naruhiko Nakanishi, Hideki Gomi
  • Patent number: RE46882
    Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: May 29, 2018
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventors: Yoshitaka Nakamura, Kenji Komeda, Ryota Suewaka, Noriaki Ikeda
  • Patent number: RE47988
    Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.
    Type: Grant
    Filed: May 28, 2018
    Date of Patent: May 12, 2020
    Assignee: Longitude Licensing Limited
    Inventors: Yoshitaka Nakamura, Kenji Komeda, Ryota Suewaka, Noriaki Ikeda