Patents by Inventor Kenji Koyama

Kenji Koyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085847
    Abstract: An image forming apparatus includes plural image holding bodies that are provided for respective colors of toners and hold toner images having the respective colors, an intermediate transfer body onto which the toner images having the respective colors held by the plural image holding bodies are transferred, a waste toner collection unit that collects toners remaining on the intermediate transfer body as a waste toner in a case where the toner images having the respective colors transferred onto the intermediate transfer body are transferred onto a recording material, a waste toner developing unit that uses the waste toner collected by the waste toner collection unit to develop a toner image on an image holding body of the plural image holding bodies or the other image holding body of the plural image holding bodies, and a control unit that performs a control to cause the waste toner developing unit to develop the toner image in a case where a predetermined condition about a ratio of a waste toner having each
    Type: Application
    Filed: March 23, 2023
    Publication date: March 14, 2024
    Applicant: FUJIFILM Business Innovation Corp.
    Inventors: Tatsuya KOYAMA, Ryo WAKAMATSU, Kenta TSUKAHIRA, Kenji SUZUKI, Kazutaka SHIBANO, Daiki KATO, Naoyuki KURITA
  • Patent number: 11842047
    Abstract: According to one embodiment, a magnetic disk device includes a power supply, a magnetic disk, a magnetic head, a communication unit that is communicable with a host computer and transmits a signal to the host computer at a first interval, a power supply monitor, a volatile memory that stores data related to read/write processing on the magnetic disk by the magnetic head, a non-volatile memory, and a controller that controls the communication unit to start processing of backing up the data stored in the volatile memory to the non-volatile memory and transmit the signal at a second interval longer than the first interval if power supplied from the power supply is detected to be disconnected based on monitoring of the power supply monitor.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: December 12, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Kenji Koyama
  • Publication number: 20230092423
    Abstract: According to one embodiment, a magnetic disk device includes a power supply, a magnetic disk, a magnetic head, a communication unit that is communicable with a host computer and transmits a signal to the host computer at a first interval, a power supply monitor, a volatile memory that stores data related to read/write processing on the magnetic disk by the magnetic head, a non-volatile memory, and a controller that controls the communication unit to start processing of backing up the data stored in the volatile memory to the non-volatile memory and transmit the signal at a second interval longer than the first interval if power supplied from the power supply is detected to be disconnected based on monitoring of the power supply monitor.
    Type: Application
    Filed: March 10, 2022
    Publication date: March 23, 2023
    Inventor: Kenji KOYAMA
  • Publication number: 20220317869
    Abstract: A storage medium storing a screen generation assisting program that causes a computer to execute a process that includes accepting, in an input screen to which information for generating a screen of a first hierarchical level is input, designation of a number of elements of a second hierarchical level that serves as a lower level than the first hierarchical level; associating a first template for generating the screen of the first hierarchical level with second templates for generating a screen of the second hierarchical level; generating the screen of the second hierarchical level by displaying the pieces of data in regions of the second templates; and generating the screen of the first hierarchical level by displaying, in region of the first template that corresponds to the regions of the second templates, a summarized value of the same number of the pieces of data of the second hierarchical level.
    Type: Application
    Filed: February 11, 2022
    Publication date: October 6, 2022
    Applicant: FUJITSU LIMITED
    Inventors: Kenji Koyama, Yuko Miyabara, Yuta Shioiri
  • Publication number: 20220299138
    Abstract: A compressor is configured to compress a fluid. The compressor includes a first casing and at least one first pipe. The first casing is electrically conductive. The at least one first pipe is electrically conductive. The at least one first pipe is fixed to the first casing with a first insulator interposed therebetween.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 22, 2022
    Inventors: Shoujirou NAKA, Kenji KOYAMA
  • Publication number: 20220154987
    Abstract: An air conditioner includes a first unit and a second unit. The first unit is connected to the second unit by a connection power wire and a connection ground wire, the connection power wire feeding power from the first unit to the second unit, the connection ground wire connecting ground of the first unit to ground of the second unit. The first unit includes a capacitor connected between the connection power wire and ground of the first unit. The connection power wire and the connection ground wire extend through a hole of a magnetic piece.
    Type: Application
    Filed: March 25, 2020
    Publication date: May 19, 2022
    Applicant: DAIKIN INDUSTRIES, LTD.
    Inventors: Masahiro YAMAMOTO, Kenji KOYAMA
  • Patent number: 8964809
    Abstract: A semiconductor optical integrated device includes a substrate having a main surface with a first and second regions arranged along a waveguiding direction; a gain region including a first cladding layer, an active layer, and a second cladding layer arranged on the first region of the main surface; and a wavelength control region including a third cladding layer, an optical waveguide layer, and a fourth cladding layer arranged on the second region of the main surface and including a heater arranged along the optical waveguide layer. The substrate includes a through hole extending from a back surface of the substrate in the thickness direction and reaching the first region. A metal member is arranged in the through hole. The metal member extends from the back surface of the substrate in the thickness direction and is in contact with the first cladding layer.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: February 24, 2015
    Assignee: Sumitomo Electric Industies, Ltd
    Inventors: Yoshihiro Yoneda, Masaki Yanagisawa, Kenji Koyama, Hirohiko Kobayashi, Kenji Hiratsuka
  • Patent number: 8637329
    Abstract: A method for producing a semiconductor optical integrated device includes the steps of forming a substrate product including first and second stacked semiconductor layer portions; forming a first mask on the first and second stacked semiconductor layer portions, the first mask including a stripe-shaped first pattern region and a second pattern region, the second pattern region including a first end edge; forming a stripe-shaped mesa structure; removing the second pattern region of the first mask; forming a second mask on the second stacked semiconductor layer portion; and selectively growing a buried semiconductor layer with the first and second masks. The second mask includes a second end edge separated from the first end edge of the first mask, the second end edge being located on the side of the second stacked semiconductor layer portion in the predetermined direction with respect to the first end edge of the first mask.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: January 28, 2014
    Assignee: Sumitomo Electric Industries Ltd
    Inventors: Yoshihiro Yoneda, Hirohiko Kobayashi, Kenji Koyama, Masaki Yanagisawa, Kenji Hiratsuka
  • Patent number: 8618638
    Abstract: A process to manufacture a semiconductor optical modulator is disclosed, in which the process easily forms a metal film including AuZn for the p-ohmic metal even a contact hole has an enhanced aspect ration. The process forms a mesa including semiconductor layers first, then, buries the mesa by a resin layer sandwiched by insulating films. The resin layer provides an opening reaching the top of the mesa, into which the p-ohmic metal is formed. Another metal film including Ti is formed on the upper insulating film along the opening.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: December 31, 2013
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: Yoshihiro Yoneda, Kenji Koyama, Hirohiko Kobayashi
  • Patent number: 8563342
    Abstract: A method of making a semiconductor optical integrated device includes the steps of forming, on a substrate, a plurality of semiconductor integrated devices including a first optical semiconductor element having a first bonding pad and a second optical semiconductor element; forming a plurality of bar-shaped semiconductor optical integrated device arrays by cutting the substrate, each of the semiconductor optical integrated device arrays including two or more semiconductor optical integrated devices; alternately arranging the plurality of semiconductor optical integrated device arrays and a plurality of spacers in a thickness direction of the substrate so as to be fixed in place; and forming a coating film on a facet of the semiconductor optical integrated device array. Furthermore, the spacer has a movable portion facing the first bonding pad, the movable portion protruding toward the first bonding pad and being displaceable in a protruding direction.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: October 22, 2013
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: Yoshihiro Yoneda, Hirohiko Kobayashi, Kenji Koyama, Masaki Yanagisawa, Kenji Hiratsuka
  • Patent number: 8530750
    Abstract: A multilayer printed circuit board includes a first conductive layer including (i) a first signal ground, (ii) a first frame ground mounted on an external interface component, (iii) a first slit portion that separates the first signal ground and the first frame ground from each other, and (iv) a signal wiring arranged to extend over the first slit portion. A second conductive layer is laminated on the first conductive layer through a dielectric layer. The second conductive layer includes (i) a second signal ground, (ii) a second frame ground, and (iii) a second slit portion that separates the second signal ground and the second frame ground from each other. A first connecting member and a second connecting member connect the second signal ground and the second frame ground to each other.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: September 10, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kenji Koyama
  • Publication number: 20130170167
    Abstract: A multi-layer printed circuit board includes an embedded capacitor substrate composed of a power source conductor layer and a ground conductor layer, the layers being disposed close to each other. The power source conductor layer has a first power source plane to supply power to a circuit element, and a second power source plane that is separated from the first power source plane by a gap and functions as a main power source. The first power source plane is partially connected to the second power source plane by a connecting line. The ground conductor layer has an opening at a position overlapping with a projected image when the connecting line is projected on the ground conductor layer. This structure suppresses propagation of the noise caused at the circuit element and reduces radiation noise in the printed circuit board.
    Type: Application
    Filed: September 16, 2011
    Publication date: July 4, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Toyohide Miyazaki, Kenji Koyama
  • Publication number: 20130058371
    Abstract: A semiconductor optical integrated device includes a substrate having a main surface with a first and second regions arranged along a waveguiding direction; a gain region including a first cladding layer, an active layer, and a second cladding layer arranged on the first region of the main surface; and a wavelength control region including a third cladding layer, an optical waveguide layer, and a fourth cladding layer arranged on the second region of the main surface and including a heater arranged along the optical waveguide layer. The substrate includes a through hole extending from a back surface of the substrate in the thickness direction and reaching the first region. A metal member is arranged in the through hole. The metal member extends from the back surface of the substrate in the thickness direction and is in contact with the first cladding layer.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 7, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yoshihiro YONEDA, Masaki YANAGISAWA, Kenji KOYAMA, Hirohiko KOBAYASHI, Kenji HIRATSUKA
  • Publication number: 20130012002
    Abstract: A method for producing a semiconductor optical integrated device includes the steps of forming a substrate product including first and second stacked semiconductor layer portions; forming a first mask on the first and second stacked semiconductor layer portions, the first mask including a stripe-shaped first pattern region and a second pattern region, the second pattern region including a first end edge; forming a stripe-shaped mesa structure; removing the second pattern region of the first mask; forming a second mask on the second stacked semiconductor layer portion; and selectively growing a buried semiconductor layer with the first and second masks. The second mask includes a second end edge separated from the first end edge of the first mask, the second end edge being located on the side of the second stacked semiconductor layer portion in the predetermined direction with respect to the first end edge of the first mask.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 10, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yoshihiro YONEDA, Hirohiko KOBAYASHI, Kenji KOYAMA, Masaki YANAGISAWA, Kenji HIRATSUKA
  • Publication number: 20120309121
    Abstract: A method of making a semiconductor optical integrated device includes the steps of forming, on a substrate, a plurality of semiconductor integrated devices including a first optical semiconductor element having a first bonding pad and a second optical semiconductor element; forming a plurality of bar-shaped semiconductor optical integrated device arrays by cutting the substrate, each of the semiconductor optical integrated device arrays including two or more semiconductor optical integrated devices; alternately arranging the plurality of semiconductor optical integrated device arrays and a plurality of spacers in a thickness direction of the substrate so as to be fixed in place; and forming a coating film on a facet of the semiconductor optical integrated device array. Furthermore, the spacer has a movable portion facing the first bonding pad, the movable portion protruding toward the first bonding pad and being displaceable in a protruding direction.
    Type: Application
    Filed: May 24, 2012
    Publication date: December 6, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yoshihiro YONEDA, Hirohiko KOBAYASHI, Kenji KOYAMA, Masaki YANAGISAWA, Kenji HIRATSUKA
  • Patent number: 8240746
    Abstract: A vehicle front body structure includes a chassis number marking section on which a chassis number or vehicle identification number (VIN) is applied by stamping. The chassis number marking section is provided on a cowl assembly and disposed above a damper base to which an end of the cowl box is secured.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: August 14, 2012
    Assignee: Honda Motor Co., Ltd.
    Inventors: Hideaki Yamagishi, Kenji Koyama
  • Publication number: 20120148184
    Abstract: A process to manufacture a semiconductor optical modulator is disclosed, in which the process easily forms a metal film including AuZn for the p-ohmic metal even a contact hole has an enhanced aspect ration. The process forms a mesa including semiconductor layers first, then, buries the mesa by a resin layer sandwiched by insulating films. The resin layer provides an opening reaching the top of the mesa, into which the p-ohmic metal is formed. Another metal film including Ti is formed on the upper insulating film along the opening.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 14, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yoshihiro Yoneda, Kenji Koyama, Hirohiko Kobayashi
  • Patent number: 8124543
    Abstract: A method for manufacturing an LD is disclosed. The LD has a striped structure including an optical active region. The striped structure is buried with resin, typically benzo-cyclo-butene (BCB). The method to form an opening in the BCB layer has tri-steps etching of the RIE. First step etches the BCB layer partially by a mixed gas of CF4 and O2, where CF4 has a first partial pressure, second step etches the photo-resist patterned on the top of the BCB layer by a mixed gas of CF4 and O2, where CF4 in this step has the second partial pressure less than the first partial pressure, and third step etches the BCB left in the first step by mixed gas of CF4 and O2, where CF4 in this step has the third partial pressure greater than the second partial pressure.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: February 28, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideki Yagi, Kenji Koyama, Hiroyuki Yoshinaga, Kuniaki Ishihara
  • Publication number: 20110247869
    Abstract: Provided is a multilayer printed circuit board including: a signal ground pattern; a frame ground pattern formed through a slit portion; an external interface component connected to a semiconductor device by a signal wiring extending over the slit portion; and two connecting members having an electrical conductivity arranged symmetrically such that the connecting members sandwich the signal wiring and extend over the slit portion. With this configuration, a return current path is formed between the frame ground pattern and the signal ground pattern, to thereby improve a resistance to exogenous noise such as electrostatic discharge noise, and suppress radiation noise.
    Type: Application
    Filed: January 28, 2010
    Publication date: October 13, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Kenji Koyama
  • Publication number: 20110084518
    Abstract: A vehicle front body structure includes a chassis number marking section on which a chassis number or vehicle identification number (VIN) is applied by stamping. The chassis number marking section is provided on a cowl assembly and disposed above a damper base to which an end of the cowl box is secured.
    Type: Application
    Filed: August 12, 2010
    Publication date: April 14, 2011
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Hideaki Yamagishi, Kenji Koyama