Patents by Inventor Kenji Kunihara

Kenji Kunihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6784511
    Abstract: In a resin-sealed laser diode device, in order to prevent the sealing resin on the front light-emitting end face of the laser diode chip from being deteriorated by the laser beam, a thermosetting rubber-like organic silicone resin layer is formed on the front light-emitting end face to a thickness of at least 50 &mgr;m on the extension of the surface of the active layer. On the side of the rear light-emitting end-face of the laser diode chip, the rubber-like organic silicone resin layer on the photo-diode is curved upwardly with respect to the light receiving surface of the latter. Furthermore, in order to prevent the far field pattern of the laser beam from being made irregular, at least the surface of the end-face protecting film on the light-emitting end face essentially contains silicon dioxide.
    Type: Grant
    Filed: October 4, 1994
    Date of Patent: August 31, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kenji Kunihara, Yoichi Shindo, Hiromi Mojikawa, Tadashi Umegaki, Satoru Nagano
  • Patent number: 6693323
    Abstract: A method of manufacture reduces costs and provides an excellent mass-productivity, a super-junction semiconductor device, that facilitates reducing times of heat treatment of the alternating conductivity type layer subjects, and preventing the characteristics of the alternating conductivity type layer from being impaired. A surface MOSFET structure, including p-type base regions, p+-type contact region in p-type base region, an n+-type source region in p-type base region, a gate electrode layer and a source electrode, is formed in the surface portion of an n-type semiconductor substrate through the usual double diffusion MOSFET manufacturing process. An oxide film is deposited by the CVD method on the back surface of the semiconductor substrate, a resist mask for defining p-type partition regions is formed on the oxide film, oxide film is removed by ion etching, and trenches are dug.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: February 17, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Takahiro Sato, Katsunori Ueno, Tatsuhiko Fujihira, Kenji Kunihara, Yasuhiko Onishi, Susumu Iwamoto
  • Publication number: 20030008483
    Abstract: A method of manufacture reduces costs and provides an excellent mass-productivity, a super-junction semiconductor device, that facilitates reducing times of heat treatment of the alternating conductivity type layer subjects, and preventing the characteristics of the alternating conductivity type layer from being impaired. A surface MOSFET structure, including p-type base regions, p+-type contact region in p-type base region, an n+-type source region in p-type base region, a gate electrode layer and a source electrode, is formed in the surface portion of an n-type semiconductor substrate through the usual double diffusion MOSFET manufacturing process. And oxide film is deposited by the CVD method on the back surface of the semiconductor substrate, a resist mask for defining p-type partition regions is formed on the oxide film, oxide film is removed by ion etching, and trenches are dug.
    Type: Application
    Filed: September 9, 2002
    Publication date: January 9, 2003
    Applicant: Fuji Electric, Co., Ltd.
    Inventors: Takahiro Sato, Katsunori Ueno, Tatsuhiko Fujihira, Kenji Kunihara, Yasuhiko Onishi, Susumu Iwamoto
  • Patent number: 6475864
    Abstract: A method of manufacturing reduces costs and provides an excellent mass-productivity, super-junction semiconductor device, which facilitates reducing times of heat treatment of the alternating conductivity type layer subjects, and preventing the characteristics of the alternating conductivity type layer from being impaired. A surface MOSFET structure, including p-type base regions, p+-type contact region in p-type base region, an n+-type source region in p-type base region, a gate electrode layer and a source electrode, is formed in the surface portion of an n-type semiconductor substrate through the usual double difflusion MOSFET manufacturing process. An oxide film is deposited by the CVD method on the back surface of the semiconductor substrate, a resist mask for defining p-type partition regions is formed on the oxide film, the oxide film is removed by ion etching, and trenches are dug.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: November 5, 2002
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Takahiro Sato, Katsunori Ueno, Tatsuhiko Fujihira, Kenji Kunihara, Yasuhiko Onishi, Susumu Iwamoto