Patents by Inventor Kenji Miyakoshi
Kenji Miyakoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9293578Abstract: Adverse effects can be hardly exerted on a current performance of an LDMOSFET to suppress the amount of carrier implantation from an anode layer of an LDMOS parasitic diode, and improve a reverse recovery withstand of the parasitic diode. The LDMOSFET includes a semiconductor substrate having a first semiconductor region formed of a feeding region of a first conductivity type at a position where a field oxide film is not present on a surface layer of a semiconductor region in which the field oxide film is selectively formed, and a second semiconductor region formed of a well region of a second conductivity type which is an opposite conductivity type, and feeding regions of the first conductivity type and the second conductivity type formed on an upper layer of the well region, and a gate electrode that faces the well region through a gate oxide film.Type: GrantFiled: July 3, 2013Date of Patent: March 22, 2016Assignee: Hitachi, Ltd.Inventors: Tomoyuki Miyoshi, Takayuki Oshima, Yohei Yanagida, Hiroki Kimura, Kenji Miyakoshi
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Publication number: 20150041883Abstract: An object of the present invention is to improve the ESD resistance of an electrostatic protection element. The essence of the basic idea resides in that an electrostatic protection element ESD is configured to include not a thyristor or an npn bipolar transistor, but a pnp bipolar transistor so as to be connected in parallel with a diode. In other words, the essence of the basic idea resides in that an electrostatic protection element ESD is constituted by a diode parasitically provided with a pnp bipolar transistor.Type: ApplicationFiled: August 6, 2014Publication date: February 12, 2015Inventors: Hiroki Kimura, Youhei Yanagida, Kenji Miyakoshi, Tomoyuki Miyoshi, Takayuki Ooshima
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Publication number: 20140284714Abstract: Disclosed is a semiconductor device that includes a first MOS transistor having a predetermined size and a second MOS transistor having a lager size than the first MOS transistor. The first MOS transistor is divided into two or more sections, each paired with a corresponding section of the second MOS transistor to form a unit cell. As the unit cell is cyclically formed on a substrate, the current mirror ratio between the total size of the first MOS transistor and the total size of the second MOS transistor remains unaffected by the nonuniformity of position-dependent temperature distribution.Type: ApplicationFiled: February 27, 2014Publication date: September 25, 2014Inventors: Kenji Miyakoshi, Youhei Yanagida, Hiroki Kimura, Takayuki Ooshima
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Patent number: 8841724Abstract: In an LDMOS transistor, a channel length is reduced to increase a saturation current without causing an off-state breakdown voltage optimized in terms of trade-off between an on-resistance and the off-state breakdown voltage. A short channel region is selectively formed between an element isolation film and a low-concentration body region in which a channel is formed such that the short channel region is located immediately below a gate oxide film. The short channel region has a conduction type opposite to that of the low-concentration body region and has a carrier concentration higher than that of the low-concentration body region. The body region is retreated by the presence of the short channel region toward a high-concentration source region.Type: GrantFiled: December 29, 2010Date of Patent: September 23, 2014Assignee: Hitachi, Ltd.Inventors: Kenji Miyakoshi, Shinichiro Wada, Yohei Yanagida, Takayuki Oshima, Keigo Kitazawa
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Publication number: 20140015049Abstract: An LDMOSFET includes a semiconductor substrate having a first semiconductor region formed of a feeding region of a first conduction type at a position where a field oxide film is not present on a surface layer of a semiconductor region in which the field oxide film is selectively formed, and a second semiconductor region formed of a well region of a second conduction type which is an opposite conduction type, and feeding regions of the first and second conduction types formed on an upper layer of the well region, and a gate electrode that faces the well region through a gate oxide film. The feeding region is formed at a distance from the field oxide film in an end portion in a longitudinal direction, and desirably the feeding region is intermittently formed at given intervals in the longitudinal direction, and the feeding region is applied to the first semiconductor region.Type: ApplicationFiled: July 3, 2013Publication date: January 16, 2014Inventors: Tomoyuki Miyoshi, Takayuki Oshima, Yohei Yanagida, Hiroki Kimura, Kenji Miyakoshi
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Patent number: 8368151Abstract: When MOS transistors having a plurality of threshold voltages in which a source and a drain form a symmetrical structure are mounted on the same substrate, electrically-symmetrical characteristics is provided with respect to an exchange of the source and the drain in each MOS transistor. A MOS transistor having a large threshold voltage is provided with a halo diffusion region, and halo implantation is not performed on a MOS transistor having a small threshold voltage.Type: GrantFiled: December 22, 2009Date of Patent: February 5, 2013Assignee: Hitachi, Ltd.Inventors: Kenji Miyakoshi, Shinichiro Wada, Junji Noguchi, Koichiro Miyamoto, Masaya Iida, Masafumi Suefuji
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Publication number: 20110215401Abstract: In an LDMOS transistor, a channel length is reduced to increase a saturation current without causing an off-state breakdown voltage optimized in terms of trade-off between an on-resistance and the off-state breakdown voltage. A short channel region is selectively formed between an element isolation film and a low-concentration body region in which a channel is formed such that the short channel region is located immediately below a gate oxide film. The short channel region has a conduction type opposite to that of the low-concentration body region and has a carrier concentration higher than that of the low-concentration body region. The body region is retreated by the presence of the short channel region toward a high-concentration source region.Type: ApplicationFiled: December 29, 2010Publication date: September 8, 2011Applicant: Hitachi, Ltd.Inventors: Kenji MIYAKOSHI, Shinichiro Wada, Yohei Yanagida, Takayuki Oshima, Keigo Kitazawa
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Publication number: 20100164015Abstract: When MOS transistors having a plurality of threshold voltages in which a source and a drain form a symmetrical structure are mounted on the same substrate, electrically-symmetrical characteristics is provided with respect to an exchange of the source and the drain in each MOS transistor. A MOS transistor having a large threshold voltage is provided with a halo diffusion region, and halo implantation is not performed on a MOS transistor having a small threshold voltage.Type: ApplicationFiled: December 22, 2009Publication date: July 1, 2010Applicant: HITACHI, LTD.Inventors: Kenji MIYAKOSHI, Shinichiro WADA, Junji NOGUCHI, Koichiro MIYAMOTO, Masaya IIDA, Masafumi SUEFUJI