Abstract: Provided are external input/output signal terminals, an interface circuit including a plurality of unit input/output circuits accompanying the respective signal terminals, a memory macro, a BIST (built-in self-test) circuit for performing a self test of the memory macro, and a logic circuit including a plurality of circuit blocks for generating various control signals. The unit input/output circuits are individually controlled by the various control signals. By externally controlling a specific one of the external input/output signal terminals, the logics of other external input/output signal terminals are individually controlled by the various internal signals.

Abstract: A semiconductor device includes: a plurality of memory macros, each of which includes a plurality of memory cells, is activated in accordance with a corresponding active macro selection signal, and operates in an active mode according to a corresponding active mode control signal; and a control unit for generating and outputting, in accordance with an input operation mode control signal, the active macro selection signals and the active mode control signals that correspond to the respective memory macros, so that two or more of the memory macros are activated simultaneously.

Abstract: A semiconductor memory device is provided which has a unit by which a fail bit map can be checked instantaneously over the entire address space. The semiconductor memory device is provided with a data logic forcefully controlling circuit 21 which forcefully controls the logic of write data into memory cells selected by using a specified address signal or of read data, a specified row forcefully controlling circuit 40 which forcefully makes the control of memory cells selected according to specified row addresses the control exercised during operation different from normal operation, or a specified column forcefully controlling circuit 50 which forcefully makes the control of memory cells selected according to specified column addresses the control exercised during operation different from normal operation. This forced fail operation mode is selectable aside from normal operation mode.

Abstract: A semiconductor device having a chip-on-chip structure wherein; a first semiconductor chip with a memory macro control circuit where a plurality of inter-chip connection terminals and a plurality of external connection terminals are formed on a surface of the chip; and a second semiconductor chip with memory macro having input/output terminals for the normal operation mode and for the test mode where a plurality of inter-chip connection terminals and a plurality of external connection terminals are formed on a surface of the chip; are adhered to each other in a form so that the surfaces of the chips are opposed to each other and so that the inter-chip connection terminals of the first semiconductor chip and the inter-chip connection terminals of the second semiconductor chip are connected to each other; is provided wherein a multiplexer circuit and a demultiplexer circuit are provided with the first semiconductor chip and the second semiconductor chip so that a signal is inputted to, or is outputted from, the

Abstract: Provided are external input/output signal terminals, an interface circuit including a plurality of unit input/output circuits accompanying the respective signal terminals, a memory macro, a BIST (built-in self-test) circuit for performing a self test of the memory macro, and a logic circuit including a plurality of circuit blocks for generating various control signals. The unit input/output circuits are individually controlled by the various control signals. By externally controlling a specific one of the external input/output signal terminals, the logics of other external input/output signal terminals are individually controlled by the various internal signals.

Abstract: A semiconductor memory device is provided which has a unit by which a fail bit map can be checked instantaneously over the entire address space. The semiconductor memory device is provided with a data logic forcefully controlling circuit 21 which forcefully controls the logic of write data into memory cells selected by using a specified address signal or of read data, a specified row forcefully controlling circuit 40 which forcefully makes the control of memory cells selected according to specified row addresses the control exercised during operation different from normal operation, or a specified column forcefully controlling circuit 50 which forcefully makes the control of memory cells selected according to specified column addresses the control exercised during operation different from normal operation. This forced fail operation mode is selectable aside from normal operation mode.

Abstract: A semiconductor device includes: a plurality of memory macros, each of which includes a plurality of memory cells, is activated in accordance with a corresponding active macro selection signal, and operates in an active mode according to a corresponding active mode control signal; and a control unit for generating and outputting, in accordance with an input operation mode control signal, the active macro selection signals and the active mode control signals that correspond to the respective memory macros, so that two or more of the memory macros are activated simultaneously.

Abstract: A semiconductor device having a chip-on-chip structure wherein; a first semiconductor chip with a memory macro control circuit where a plurality of inter-chip connection terminals and a plurality of external connection terminals are formed on a surface of the chip; and a second semiconductor chip with memory macro having input/output terminals for the normal operation mode and for the test mode where a plurality of inter-chip connection terminals and a plurality of external connection terminals are formed on a surface of the chip; are adhered to each other in a form so that the surfaces of the chips are opposed to each other and so that the inter-chip connection terminals of the first semiconductor chip and the inter-chip connection terminals of the second semiconductor chip are connected to each other; is provided wherein a multiplexer circuit and a demultiplexer circuit are provided with the first semiconductor chip and the second semiconductor chip so that a signal is inputted to, or is outputted from, the