Patents by Inventor Kenji NAKAGOMI
Kenji NAKAGOMI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10879858Abstract: An oscillator circuit uses a comparator, and the oscillator circuit controls charge-discharge of the Miller capacitance between the gate and the drain of a MOSFET serving as an amplifier of the gain unit and the gate capacitance of the MOSFET, and enables the comparator output to follow a relatively high-frequency control signal that is input externally. The oscillator circuit uses a comparator having a differential unit and a gain unit. The oscillator circuit includes a charge-discharge control unit that connects to the output of the differential unit and is configured to control charge-discharge of the Miller capacitance between the gate and the drain of a MOSFET (N2) serving as an amplifier of the gain unit and the gate capacitance of the MOSFET, and an output control unit configured to control the output of the gain unit.Type: GrantFiled: September 25, 2019Date of Patent: December 29, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventor: Kenji Nakagomi
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Patent number: 10771046Abstract: Oscillator circuit uses a comparator, and controls charge-discharge of Miller capacitance between gate and drain of a MOSFET serving as an amplifier of the comparator gain unit and gate capacitance of the MOSFET, and enables comparator output to follow a high-frequency control signal that is input externally. An oscillator circuit uses a comparator CMP having differential and gain units. This oscillator circuit includes: a charge-discharge controller to control charge-discharge of Miller capacitance between gate and drain of a MOSFET and gate capacitance of the MOSFET; and an output controller to control output of the gain unit. Output controller includes: an inverter to connect to an input of the differential unit and receive a control signal input; a logic circuit to receive output of the inverter and output of the gain unit as an input; a transistor; and a capacitor to connect to input and output of the logic circuit.Type: GrantFiled: December 2, 2019Date of Patent: September 8, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventor: Kenji Nakagomi
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Publication number: 20200106427Abstract: Oscillator circuit uses a comparator, and controls charge-discharge of Miller capacitance between gate and drain of a MOSFET serving as an amplifier of the comparator gain unit and gate capacitance of the MOSFET, and enables comparator output to follow a high-frequency control signal that is input externally. An oscillator circuit uses a comparator CMP having differential and gain units. This oscillator circuit includes: a charge-discharge controller to control charge-discharge of Miller capacitance between gate and drain of a MOSFET and gate capacitance of the MOSFET; and an output controller to control output of the gain unit. Output controller includes: an inverter to connect to an input of the differential unit and receive a control signal input; a logic circuit to receive output of the inverter and output of the gain unit as an input; a transistor; and a capacitor to connect to input and output of the logic circuit.Type: ApplicationFiled: December 2, 2019Publication date: April 2, 2020Applicant: FUJI ELECTRIC CO., LTD.Inventor: Kenji NAKAGOMI
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Publication number: 20200021258Abstract: An oscillator circuit uses a comparator, and the oscillator circuit controls charge-discharge of the Miller capacitance between the gate and the drain of a MOSFET serving as an amplifier of the gain unit and the gate capacitance of the MOSFET, and enables the comparator output to follow a relatively high-frequency control signal that is input externally. The oscillator circuit uses a comparator having a differential unit and a gain unit. The oscillator circuit includes a charge-discharge control unit that connects to the output of the differential unit and is configured to control charge-discharge of the Miller capacitance between the gate and the drain of a MOSFET (N2) serving as an amplifier of the gain unit and the gate capacitance of the MOSFET, and an output control unit configured to control the output of the gain unit.Type: ApplicationFiled: September 25, 2019Publication date: January 16, 2020Applicant: FUJI ELECTRIC CO., LTD.Inventor: Kenji NAKAGOMI
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Patent number: 10277106Abstract: A control circuit 2a for a switching power supply apparatus includes a comparator COMPa for comparing a voltage corresponding to a current flowing through a switching element PT1 with a voltage to be compared therewith, and outputting a comparison signal corresponding to a result of the comparison. To the comparator, a blanking pulse signal is also input. Here, the blanking pulse signal indicates whether or not it is currently in a predetermined period that is set for ensuring that the switching element is not turned off for the predetermined period after the switching element has been turned on. When the blanking pulse signal indicates that it is currently in the predetermined period, the comparison signal is set to low level independently of the voltage corresponding to the current and the voltage to be compared therewith.Type: GrantFiled: June 30, 2017Date of Patent: April 30, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventor: Kenji Nakagomi
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Patent number: 10020804Abstract: An output stage buffer circuit including a first P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), first to third N-channel MOSFETs, a constant-voltage circuit and a bias circuit. A source of the first P-channel MOSFET is connected to a power supply terminal. A source and a drain of the first N-channel MOSFET are respectively connected to a ground terminal and an output terminal. The first N-channel and P-channel MOSFETs constitute a push-pull circuit. The second N-channel MOSFET is disposed between a drain of the first P-channel MOSFET and a connection point between the drain of the first N-channel MOSFET and the output terminal. A source and a drain of the third N-channel MOSFET respectively receive from the constant-voltage circuit a constant voltage lower than a voltage received at the power supply terminal, and from the bias circuit a constant current. The second and third N-channel MOSFETs constitute a current mirror circuit.Type: GrantFiled: July 28, 2017Date of Patent: July 10, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventor: Kenji Nakagomi
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Publication number: 20180091139Abstract: An output stage buffer circuit including a first P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), first to third N-channel MOSFETs, a constant-voltage circuit and a bias circuit. A source of the first P-channel MOSFET is connected to a power supply terminal. A source and a drain of the first N-channel MOSFET are respectively connected to a ground terminal and an output terminal. The first N-channel and P-channel MOSFETs constitute a push-pull circuit. The second N-channel MOSFET is disposed between a drain of the first P-channel MOSFET and a connection point between the drain of the first N-channel MOSFET and the output terminal. A source and a drain of the third N-channel MOSFET respectively receive from the constant-voltage circuit a constant voltage lower than a voltage received at the power supply terminal, and from the bias circuit a constant current. The second and third N-channel MOSFETs constitute a current mirror circuit.Type: ApplicationFiled: July 28, 2017Publication date: March 29, 2018Applicant: FUJI ELECTRIC CO., LTD.Inventor: Kenji NAKAGOMI
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Publication number: 20180019657Abstract: A control circuit 2a for a switching power supply apparatus includes a comparator COMPa for comparing a voltage corresponding to a current flowing through a switching element PT1 with a voltage to be compared therewith, and outputting a comparison signal corresponding to a result of the comparison. To the comparator, a blanking pulse signal is also input. Here, the blanking pulse signal indicates whether or not it is currently in a predetermined period that is set for ensuring that the switching element is not turned off for the predetermined period after the switching element has been turned on. When the blanking pulse signal indicates that it is currently in the predetermined period, the comparison signal is set to low level independently of the voltage corresponding to the current and the voltage to be compared therewith.Type: ApplicationFiled: June 30, 2017Publication date: January 18, 2018Applicant: FUJI ELECTRIC CO., LTD.Inventor: Kenji NAKAGOMI
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Patent number: 9515624Abstract: A differential amplifier includes a differential circuit section, a gain circuit section amplifying the output of the differential circuit section and outputting the amplified output, and an offset voltage adjusting circuit section carrying out an adjustment so that a voltage equal to the offset voltage of the differential circuit section is added to the input voltage applied across a pair of input terminals and giving the adjusted voltage to the differential circuit section. The offset voltage adjusting circuit section includes a differential pair formed of a pair of MOS-FETs, a MOS-FET forming the load of the differential pair, and two resistor elements each corresponding to one of the MOS-FETs of the differential pair and the load, and giving a voltage equal to the offset voltage to the differential pair. This provides a differential amplifier suitable for detecting the output current of the zero-phase current transformer in an earth leakage breaker.Type: GrantFiled: April 11, 2014Date of Patent: December 6, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventor: Kenji Nakagomi
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Publication number: 20140306759Abstract: A differential amplifier includes a differential circuit section, a gain circuit section amplifying the output of the differential circuit section and outputting the amplified output, and an offset voltage adjusting circuit section carrying out an adjustment so that a voltage equal to the offset voltage of the differential circuit section is added to the input voltage applied across a pair of input terminals and giving the adjusted voltage to the differential circuit section. The offset voltage adjusting circuit section includes a differential pair formed of a pair of MOS-FETs, a MOS-FET forming the load of the differential pair, and two resistor elements each corresponding to one of the MOS-FETs of the differential pair and the load, and giving a voltage equal to the offset voltage to the differential pair. This provides a differential amplifier suitable for detecting the output current of the zero-phase current transformer in an earth leakage breaker.Type: ApplicationFiled: April 11, 2014Publication date: October 16, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventor: Kenji NAKAGOMI