Abstract: In a nonvolatile semiconductor device in which source metal interconnections for coupling to ground a source of a floating gate type memory transistor are commonly provided for each predetermined plurality of memory transistors, switching transistors are provided for each column for coupling to ground columns excluding the selected column when a single column is selected in response to an external column address. Each of the switching transistors operates in response to an inverted signal of an output of a column decoder. According to this structure, a variation in source potential of each memory transistor caused by the difference in source resistance associated with each of the memory transistors is reduced.

Abstract: A semiconductor memory device having an error checking and correcting (ECC) circuit is disclosed. This memory device includes data lines (10-21) from an ECC data generation circuit and bit lines (30-41) connected to the adjacent memory cells in a memory array (1), which are selectively connected at specified connecting portions (51, 52). When predetermined test data is inputted in order to detect undesired contact or interference between the memory cells, checker pattern data can be written in all the memory cells. Thus, despite the fact that the memory device includes an ECC circuit, a complete and easy memory cell checking is carried out.

Abstract: A method for producing a mask ROM having an array of memory cells in which pn junctions obtained by introducing P-type impurities by ion implantation onto the surface of an N-type electrically conductive layers obtained in turn by introducing N-type impurities into the polysilicon layers are formed as memory cells in a matrix configuration. The polysilicon layers that are to be rendered into the N-type electrically conductive layers are previously monocrystallized by laser annealing. In this manner, the N-type electrically conductive layers into which P-type impurities are introduced by ion implantation at the time of formation of the pn junction are turned into a monocrystalline layer so that the surface of the N-type electrically conductive layers may be uniformly and easily converted into the P-type by this ion implantation. In short, the junction surface of the pn junction used as the memory cell becomes uniform.

Abstract: An EPROM as a nonvolatile semiconductor memory device includes a semiconductor substrate 1, a gate oxide layer 3 formed on the surface of the semiconductor substrate 1, a plurality of floating gates 4a and 4b formed on the gate oxide layer 3 so as to overlap one another at the portions 4ab thereof with a gate oxide layer 14 sandwiched between the overlapping portions 4ab, and control gate strips 5 formed on a gate oxide layer 6 which overlies the floating gates 4a and 4b.

Abstract: In a nonvolatile semiconductor device in which source metal interconnections for coupling to ground a source of a floating gate type memory transistor are commonly provided for each predetermined plurality of memory transistors, switching transistors are provided for each column for coupling to ground columns excluding the selected column when a single column is selected in response to an external column address. Each of the switching transistors operates in response to an inverted signal of an output of a column decoder. According to this structure, a variation in source potential of each memory transistor caused by the difference in source resistance associated with each of the memory transistors is reduced.

Abstract: Each column latch circuit latches a potential of each bit line and that of each control gate line before information is written in a memory cell. Thus, so-called page mode writing can be performed. A column latch circuit comprises two inverters of the same polarity and statically latches an input potential. As a result, chip size can be reduced without any leakage of an electric charge representing information. Reduction of operating current requirements is also achieved by the use of inverters of the same polarity in combination with control of at least one transistor within each of the two inverters.

Abstract: A non-volatile memory cell includes a MOS transistor of double gate construction. The MOS memory transistor includes a floating gate structure which includes electrically separated first and second segmented floating gates (4a; 4b). For the purpose of writing data, electrons are independently injected into the first and second segmented floating gates. Data are stored in the MOS memory transistor in three different non-volatile storage levels; one with electron accumulated either one of the two segmented floating gates; another with electrons injected into both of the segmented floating gates; and still another with no electrons accumulated on both of the segmented floating gates.

Abstract: An EEPROM having an ECC circuit further comprises a counter circuit. The ECC circuit checks and corrects bit errors included in data read out from a memory cell array. In addition, the ECC circuit generates a predetermined signal every time it corrects a bit error. The counter circuit counts a predetermined signal generated from the ECC circuit.

Abstract: Memory transistors are arranged in a plurality of rows and a plurality of columns. A source line is formed for every two bit lines formed in the column direction, each connected to the memory transistors of one column. A source region of each memory transistor is connected, on one side, to a source line adjacent thereto and, on the other side, to a source line through the source region of the adjacent memory transistor, through impurity regions respectively. A floating gate is formed to extend to a position under the corresponding source line. In another example, a source line is formed for each bit line formed in the column direction. The source region of each memory transistor is connected to the adjacent source lines on both sides thereof through impurity regions. The floating gate is formed to extend to positions under both adjacent source lines.

Abstract: A molten lead alloy is supplied from a melting furnace to a casting machine through a feed pipe having a pair of ends connected with the furnace and the machine, respectively, and an intermediate portion situated at a level which is higher than the higher of the two levels of the molten alloy located adjacent to the ends, respectively, of the feed pipe by a distance exceeding the height of a column of the molten alloy which atmospheric pressure can support. An apparatus for supplying the molten alloy in such a way is also disclosed.

Abstract: In an EEPROM capable of writing data in a page mode, an output portion of a Y decoder is provided with a column latch circuit for storing a Y gate line selected by a Y decoder at the time of writing data. The column latch circuit activates the Y gate line selected in response to the stored information at the cycle of verifying erasing and connects a memory cell connected to the Y gate line to a data output line. Thus, it can be determined whether the erased memory cell was surely erased or not in a page mode.

Abstract: An electrophotographic litho printing plate material which has a high storage stability and is useful for providing litho printing plates having an enhanced high quality image-forming durability, an improved printing durability, and an excellent dimensional stability, comprises (A) a substrate sheet; (B) an intermediate coating layer comprising (a) wet ground white mica fine particles having an average size of 5 to 50 .mu.m, (b) a waterproofing agent comprising an organic silane compound of the formula (1): R.sub.n SiX.sub.4-n (1) wherein n=1 or 2, R=aliphatic, cycloaliphatic, aromatic or heterocyclic radical having 1 to 30 carbon atoms, at least one R being chemically reactive, and X=hydrolyzable substituent, and (c) a thermoplastic resin binder; and (C) a photoconductive coating layer containing photoconductive pigment particles and an electrically insulating polymeric binder.