Patents by Inventor Kenji Nukui
Kenji Nukui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9620616Abstract: A method of manufacturing a semiconductor device includes laminating and forming an electron transit layer, an electron supplying layer, an etching stop layer, and a p-type film on a substrate sequentially, the p-type film being formed of a nitride semiconductor material that includes Al doped with an impurity element that attains p-type, the etching stop layer being formed of a material that includes GaN, removing the p-type film in an area except an area where a gate electrode is to be formed, by dry etching to form a p-type layer in the area where the gate electrode is to be formed, the dry etching being conducted while plasma emission in the dry etching is observed, the dry etching being stopped after the dry etching is started and plasma emission originating from Al is not observed, and forming the gate electrode on the p-type layer.Type: GrantFiled: December 24, 2014Date of Patent: April 11, 2017Assignee: Transphorm Japan, Inc.Inventors: Atsushi Yamada, Kenji Nukui
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Patent number: 9142658Abstract: A compound semiconductor device includes: a compound semiconductor layer; and a gate electrode formed above the compound semiconductor layer; and a source electrode and a drain electrode formed on both sides of the gate electrode, on the compound semiconductor layer, wherein the source electrode has a plurality of bottom surfaces along transit electrons out of contact surfaces with the compound semiconductor layer, and the plural bottom surfaces are located at different distances from the transit electrons, with the bottom surface closer to the gate electrode being more apart from the transit electrons.Type: GrantFiled: September 20, 2013Date of Patent: September 22, 2015Assignee: Transphorm Japan, Inc.Inventors: Toshihide Kikkawa, Kenji Nukui
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Patent number: 9099545Abstract: A compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the gate electrode is formed of a first opening filled with a first conductive material via at least a gate insulator, and the first opening is formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the source electrode and the drain electrode are formed of a pair of second openings filled with at least a second conductive material, and the second openings are formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer.Type: GrantFiled: September 23, 2013Date of Patent: August 4, 2015Assignee: Transphorm Japan, Inc.Inventors: Shinichi Akiyama, Kenji Nukui, Mutsumi Katou, Yoshitaka Watanabe, Tetsuya Itou, Yoichi Fujisawa, Toshiya Sato, Tsutomu Hosoda, Yuuichi Satou
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Publication number: 20150137184Abstract: A method of manufacturing a semiconductor device includes laminating and forming an electron transit layer, an electron supplying layer, an etching stop layer, and a p-type film on a substrate sequentially, the p-type film being formed of a nitride semiconductor material that includes Al doped with an impurity element that attains p-type, the etching stop layer being formed of a material that includes GaN, removing the p-type film in an area except an area where a gate electrode is to be formed, by dry etching to form a p-type layer in the area where the gate electrode is to be formed, the dry etching being conducted while plasma emission in the dry etching is observed, the dry etching being stopped after the dry etching is started and plasma emission originating from Al is not observed, and forming the gate electrode on the p-type layer.Type: ApplicationFiled: December 24, 2014Publication date: May 21, 2015Inventors: Atsushi Yamada, Kenji Nukui
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Patent number: 8957453Abstract: A method of manufacturing a semiconductor device includes laminating and forming an electron transit layer, an electron supplying layer, an etching stop layer, and a p-type film on a substrate sequentially, the p-type film being formed of a nitride semiconductor material that includes Al doped with an impurity element that attains p-type, the etching stop layer being formed of a material that includes GaN, removing the p-type film in an area except an area where a gate electrode is to be formed, by dry etching to form a p-type layer in the area where the gate electrode is to be formed, the dry etching being conducted while plasma emission in the dry etching is observed, the dry etching being stopped after the dry etching is started and plasma emission originating from Al is not observed, and forming the gate electrode on the p-type layer.Type: GrantFiled: July 30, 2013Date of Patent: February 17, 2015Assignee: Transphorm Japan, Inc.Inventors: Atsushi Yamada, Kenji Nukui
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Publication number: 20140091365Abstract: A compound semiconductor device includes: a compound semiconductor layer; and a gate electrode formed above the compound semiconductor layer; and a source electrode and a drain electrode formed on both sides of the gate electrode, on the compound semiconductor layer, wherein the source electrode has a plurality of bottom surfaces along transit electrons out of contact surfaces with the compound semiconductor layer, and the plural bottom surfaces are located at different distances from the transit electrons, with the bottom surface closer to the gate electrode being more apart from the transit electrons.Type: ApplicationFiled: September 20, 2013Publication date: April 3, 2014Applicants: FUJITSU SEMICONDUCTOR LIMITED, FUJITSU LIMITEDInventors: Toshihide Kikkawa, Kenji Nukui
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Publication number: 20140091319Abstract: A method of manufacturing a semiconductor device includes laminating and forming an electron transit layer, an electron supplying layer, an etching stop layer, and a p-type film on a substrate sequentially, the p-type film being formed of a nitride semiconductor material that includes Al doped with an impurity element that attains p-type, the etching stop layer being formed of a material that includes GaN, removing the p-type film in an area except an area where a gate electrode is to be formed, by dry etching to form a p-type layer in the area where the gate electrode is to be formed, the dry etching being conducted while plasma emission in the dry etching is observed, the dry etching being stopped after the dry etching is started and plasma emission originating from Al is not observed, and forming the gate electrode on the p-type layer.Type: ApplicationFiled: July 30, 2013Publication date: April 3, 2014Applicants: Fujitsu Semiconductor Limited, Fujitsu LimitedInventors: Atsushi Yamada, KENJI NUKUI
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Publication number: 20140021513Abstract: A compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the gate electrode is formed of a first opening filled with a first conductive material via at least a gate insulator, and the first opening is formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the source electrode and the drain electrode are formed of a pair of second openings filled with at least a second conductive material, and the second openings are formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer.Type: ApplicationFiled: September 23, 2013Publication date: January 23, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shinichi AKIYAMA, Kenji NUKUI, Mutsumi KATOU, Yoshitaka WATANABE, Tetsuya ITOU, Yoichi FUJISAWA, Toshiya SATO, Tsutomu HOSODA, Yuuichi SATOU
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Patent number: 8569124Abstract: A compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the gate electrode is formed of a first opening filled with a first conductive material via at least a gate insulator, and the first opening is formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the source electrode and the drain electrode are formed of a pair of second openings filled with at least a second conductive material, and the second openings are formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer.Type: GrantFiled: April 19, 2011Date of Patent: October 29, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Shinichi Akiyama, Kenji Nukui, Mutsumi Katou, Yoshitaka Watanabe, Tetsuya Itou, Yoichi Fujisawa, Toshiya Sato, Tsutomu Hosoda, Yuuichi Satou
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Publication number: 20110272742Abstract: A compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the gate electrode is formed of a first opening filled with a first conductive material via at least a gate insulator, and the first opening is formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the source electrode and the drain electrode are formed of a pair of second openings filled with at least a second conductive material, and the second openings are formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer.Type: ApplicationFiled: April 19, 2011Publication date: November 10, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shinichi AKIYAMA, Kenji Nukui, Mutsumi Katou, Yoshitaka Watanabe, Tetsuya Itou, Yoichi Fujisawa, Toshiya Sato, Tsutomu Hosoda, Yuuichi Satou
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Patent number: 7682983Abstract: A manufacturing method of an electronic device, includes the steps of: implanting P (phosphorous) ions into a substrate semiconductor region made of Si or SiGe by using a resist as a mask; ashing the resist while it is heated in a vacuum environment; and taking out the substrate, the substrate being ashing processed so that a temperature of the substrate is equal to or less than 130° C.Type: GrantFiled: July 17, 2006Date of Patent: March 23, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Hikaru Kokura, Kenji Nukui, Shinji Fukuta, Tadashi Oshima, Fukashi Harada, Tatsuro Kawabata
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Publication number: 20070173066Abstract: A manufacturing method of an electronic device, includes the steps of: implanting P (phosphorous) ions into a substrate semiconductor region made of Si or SiGe by using a resist as a mask; ashing the resist while it is heated in a vacuum environment; and taking out the substrate, the substrate being ashing processed so that a temperature of the substrate is equal to or less than 130° C.Type: ApplicationFiled: July 17, 2006Publication date: July 26, 2007Applicant: FUJITSU LIMITEDInventors: Hikaru Kokura, Kenji Nukui, Shinji Fukuta, Tadashi Oshima, Fukashi Harada, Tatsuro Kawabata
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Patent number: 6232663Abstract: A semiconductor device and a method of fabricating thereof, including an insulator layer having alternately layered insulator films and boundary layers, wherein the boundary layers are more dense than the insulator films to prevent expansion and elongation of string-like defects across the boundary layers. The method includes mixing a nitrogen containing gas and a silane group gas to form an insulator film; temporarily stopping a flow of the silane group gas for approximately one to fifteen seconds to form a boundary layer over the insulator film; restarting the flow of the silane group gas; and repeating the steps of temporarily stopping and restarting for a predetermined number of times to form the plurality of alternately layered insulator films and boundary layers. The plurality of alternately layered insulator films and boundary layers is also etched at an etching rate for the insulator films greater than an etching rate for the boundary layers to form a step-shaped sloped opening.Type: GrantFiled: August 1, 1997Date of Patent: May 15, 2001Assignees: Fujitsu Limited, Advanced Micro Devices, Inc., Fujitsu AMD, Semiconductor LimitedInventors: Toshio Taniguchi, Kenji Nukui, Ibrahim Burki, Richard Huang, Simon Chan, Kazunori Imaoka, Kazutoshi Mochizuki