Abstract: A method and system for stabilizing a laser to a frequency reference with an adjustable offset. The method locks a sideband signal generated by passing an incoming laser beam through the phase modulator to a frequency reference, and adjusts a carrier frequency relative to the locked sideband signal by changing a phase modulation frequency input to the phase modulator. The sideband signal can be a single sideband (SSB), dual sideband (DSB), or an electronic sideband (ESB) signal. Two separate electro-optic modulators can produce the DSB signal. The two electro-optic modulators can be a broadband modulator and a resonant modulator. With a DSB signal, the method can introduce two sinusoidal phase modulations at the phase modulator. With ESB signals, the method can further drive the optical phase modulator with an electrical signal with nominal frequency ?1 that is phase modulated at a frequency ?2.

Abstract: An endoscope apparatus includes: a reading unit which reads video data and control data from a recording medium, the recording medium containing the video data including a plurality of image data and the control data used to control a measurement operation; a measuring unit which performs the measurement operation on the basis of the image data of the video data read by the reading unit; and a control unit which controls the measuring unit on the basis of the control data read by the reading unit.

Abstract: A method and system for stabilizing a laser to a frequency reference with an adjustable offset. The method locks a sideband signal generated by passing an incoming laser beam through the phase modulator to a frequency reference, and adjusts a carrier frequency relative to the locked sideband signal by changing a phase modulation frequency input to the phase modulator. The sideband signal can be a single sideband (SSB), dual sideband (DSB), or an electronic sideband (ESB) signal. Two separate electro-optic modulators can produce the DSB signal. The two electro-optic modulators can be a broadband modulator and a resonant modulator. With a DSB signal, the method can introduce two sinusoidal phase modulations at the phase modulator. With ESB signals, the method can further drive the optical phase modulator with an electrical signal with nominal frequency ?1 that is phase modulated at a frequency ?2.

Abstract: A nondestructive inspection device nondestructively inspects an internal state of an inspection target, and transmits information indicating a progress status of the inspection to the outside of an inspection site. A nondestructive inspection system which uses this nondestructive inspection device includes a network connected to the nondestructive inspection device, and one or a plurality of computers connected via the network to the nondestructive inspection device.

Abstract: A nondestructive inspection device nondestructively inspects an internal state of an inspection target, and transmits information indicating a progress status of the inspection to the outside of an inspection site. A nondestructive inspection system which uses this nondestructive inspection device includes a network connected to the nondestructive inspection device, and one or a plurality of computers connected via the network to the nondestructive inspection device.

Abstract: A semiconductor integrated circuit including a region of a memory macro function block is divided into memory core function block and interface function block regions. The interface function block includes a test circuit, a command decoder for a test, an address decoder for the test, a memory core input/output circuit which inputs a command and address into the memory core function block and transmits!receives data with the memory core function block, a configuration memory block in which information of a memory capacity of the memory core function block and configuration of a memory core is stored, and a configuration memory block which controls a data path and address path of the memory core function block based on the stored information.

Abstract: A region of a memory macro function block is divided into memory core function block and interface function block regions. The interface function block includes a test circuit, a command decoder for a test, an address decoder for the test, a memory core input/output circuit which inputs a command and address into the memory core function block and transmits/receives data with the memory core function block, a configuration memory block in which information of a memory capacity of the memory core function block and configuration of a memory core is stored, and a configuration memory block which controls a data path and address path of the memory core function block based on the stored information.

Abstract: Here is disclosed a dynamic semiconductor memory of high integration density, which has parallel word lines and parallel bit lines formed on a substrate. The bit lines include a pair of bit lines. A memory cell is coupled to a word line and to one bit line of the bit-line pair. The memory cell is composed of MOSFETs of a submicron size. A sense amplifier section is connected to the pair of bit lines, and senses and amplifies the potential difference between the pair of bit lines in a data readout mode. The amplifier section has a BIMOS structure, having MOSFETs and bipolar transistors. It has a driver section comprised of bipolar transistors.

Abstract: A program development apparatus is provided with a generator and a compiler for generating a program and an event pseudo-generating routine based on a state-transition matrix and event pseudo-generating information, an evaluation chip for executing emulation of the program and the event pseudo-generating routine and an analysis section for starting emulation of the program from a state input as an initial state, for referring to the event pseudo-generating information and for rewriting information memorized in a RAM used in executing the pseudo-generating routine and pseudo-generating an event into information corresponding to an event instructed so as to occur.

Abstract: A semiconductor integrated circuit device is described. The semiconductor device includes a switching signal generator having an output terminal which outputs a switching signal to change refresh modes. The semiconductor device also includes a first address buffer having an output terminal which outputs a first address signal, a second address buffer having an output terminal which outputs a second signal, a decoder having a first input terminal which receives the first address signal and having a second input terminal, a sense amplifier controller having an input terminal, and a switch having a first input terminal which receives the switching signal, a second input terminal which receives the second address signal, a first output terminal which outputs the second address signal to the second input terminal of the decoder and a second output terminal which outputs the second address signal to the input terminal of the sense amplifier controller, the switch being controlled by the switching signal.

Abstract: A semiconductor memory device includes a cell array having a plurality of memory cells grouped into a plurality of cell blocks and arranged in a matrix form, a plurality of word lines, a plurality of bit lines, bit line sense amplifiers (S/A), a cell block selection circuit,a plurality of data I/O lines, row decoders, a plurality of column selection signal lines, column decoders and a data buffer circuit.

Abstract: A semiconductor integrated circuit device capable of changing the product specification. The semiconductor integrated circuit device includes an integrated circuit section containing a first circuit section having a first function and a second circuit section having a second function, and an active signal generator means for producing an active signal for activating the first circuit section or the second circuit section. To change the product specification, the integrated circuit device further includes a receiving for taking in a decision signal for determining the product specification a, switching signal generator, connected to the receiving device, for producing a switching signal for changing the product specification based on the decision signal, and switching device which receives the active signal and the switching signal, and which, based on the switching signal, changes the supply of the active signal to either the first circuit section or to the second circuit section.

Abstract: According to this invention, a well region is formed on a semiconductor substrate. An n.sup.+ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N.sup.+ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p.sup.+ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential.

Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of pairs of bit lines to each of which the plurality of memory cells arranged in the column direction are connected, a plurality of latch type amplifiers each of which is provided between the bit lines of a corresponding one of the bit line pairs to amplify a potential difference between the bit lines, a plurality of activation circuits for respectively activating the plurality of latch type amplifiers, a data bus acting as passages of input data, a plurality of latch type storage circuits each of which is provided on a corresponding one of the columns and connected to the data bus, for temporarily storing the input data, a plurality of transfer gates for transferring the input data from the latch type storage circuits to the latch type amplifiers, and a transfer control circuit for controlling the transfer gates to simultaneously transfer the input data from the latch type s

Abstract: A semiconductor memory device includes a cell array having a plurality of memory cells grouped into a plurality of cell blocks and arranged in a matrix form, a plurality of word lines, a plurality of bit lines, bit line sense amplifiers (S/A), a cell block selection circuit, a plurality of data I/O lines, row decoders, a plurality of column selection signal lines, column decoders and a data buffer circuit.

Abstract: A semiconductor memory device includes a buffer for outputting an address signal and a decoding circuit having an input for receiving the address signal. A switch electrically connects the buffer to the input of the decoding circuit if a refresh mode specifying signal specifies a first data refresh mode, and electrically disconnects the buffer from the input of the decoding circuit if the refresh mode specifying signal specifies a second data refresh mode different from the first data refresh mode. An activating/deactivating circuit activates the input of the decoding circuit if the refresh mode specifying signal specifies the first data refresh mode and deactivates the input of the decoding circuit if the refresh mode specifying signal specifies the second data refresh mode.

Abstract: A semiconductor memory device includes a memory cell array, row decoder, bit line pairs, sense amplifier, sense amplifier control circuit, data latch, transfer gate, transfer gate control circuit, and write circuit. The memory cell array has dynamic memory cells arranged in an array form. The row decoder decodes a row address signal to select a desired one of rows of the memory cell array. Each of the bit line pairs is connected to those of the memory cells which are arranged on a corresponding one of columns of the memory cell array. The sense amplifier amplifies data read out on the paired bit lines and positively feeding data back to the paired bit lines to hold the data. The sense amplifier control circuit controls the operation of the sense amplifier. The data latch latches readout data and write data. The transfer gate transfers data between the data latch and the sense amplifier. The transfer gate control circuit controls the transfer gate.

Abstract: A semiconductor memory device includes a cell array having a plurality of memory cells grouped into a plurality of cell blocks and arranged in a matrix form, a plurality of word lines, a plurality of bit lines, bit line sense amplifiers (S/A), a cell block selection circuit, a plurality of data I/O lines, row decoders, a plurality of column selection signal lines, column decoders and a data buffer circuit.

Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of pairs of bit lines to each of which the plurality of memory cells arranged in the column direction are connected, a plurality of latch type amplifiers each of which is provided between the bit lines of a corresponding one of the bit line pairs to amplify a potential difference between the bit lines, a plurality of activation circuits for respectively activating the plurality of latch type amplifiers, a data bus acting as passages of input data, a plurality of latch type storage circuits each of which is provided on a corresponding one of the columns and connected to the data bus, for temporarily storing the input data, a plurality of transfer gates for transferring the input data from the latch type storage circuits to the latch type amplifiers, and a transfer control circuit for controlling the transfer gates to simultaneously transfer the input data from the latch type s

Abstract: A semiconductor memory comprises a dynamic type memory cell array arranged to form a matrix and provided with word lines commonly connected to memory cells of respective columns and bit lines commonly connected to memory cells of respective rows, a dummy cell section having a first set of dummy word lines connected to respective complimentary bit line pairs of said memory cell array by way of respective first capacitances and a second set of dummy word lines connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances, a dummy word line potential control circuit capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.