Abstract: A nonvolatile semiconductor memory has a memory cell structure with a doped semiconductor substrate, a gate electrode, a channel area disposed in the substrate below the gate electrode, a pair of variable resistance areas disposed on opposite sides of the channel area in the substrate, charge storage bodies formed above the variable resistance areas and on the sides of the gate electrode, and highly doped source and drain areas formed on opposite sides of the variable resistance areas in the substrate. The variable resistance areas are doped at a carrier concentration of 5×1017 cm?3 or less to ensure an adequate current difference between the programmed and erased states of the memory cell. The doping of the variable resistance areas differs from the lightly doped drain doping in peripheral circuit areas.

Abstract: A nonvolatile semiconductor memory has a memory cell structure with a doped semiconductor substrate, a gate electrode, a channel area disposed in the substrate below the gate electrode, a pair of variable resistance areas disposed on opposite sides of the channel area in the substrate, charge storage bodies formed above the variable resistance areas and on the sides of the gate electrode, and highly doped source and drain areas formed on opposite sides of the variable resistance areas in the substrate. The variable resistance areas are doped at a carrier concentration of 5×1017 cm?3 or less to ensure an adequate current difference between the programmed and erased states of the memory cell. The doping of the variable resistance areas differs from the lightly doped drain doping in peripheral circuit areas.

Abstract: A semiconductor memory device with improved characteristics in a reading operation is disclosed. This semiconductor memory device has: a first diffused region disposed within a semiconductor substrate; a gate dielectric spaced apart from the first diffused region, and overlying the semiconductor substrate; a gate electrode overlying the gate dielectric; a first multilayer disposed between the first diffused region and the gate dielectric, and overlying the semiconductor substrate; and a third diffused region disposed adjacent to the first multilayer within the semiconductor substrate, and doped with dopant at lower concentration than the first diffused region. The first multilayer accumulates a first charge (electron, for example), and subsequently accumulates a second charge (hole, for example) having a polarity that is opposite to the first charge, in a programming operation.