Abstract: In a phase-locked loop type synthesizer comprising a phase-locked loop which comprises a phase comparator, a loop filter, a voltage controlled oscillator having a gain Kv, and a circuit for feeding back an output from the voltage controlled oscillator to the phase comparator through a frequency divider having a frequency division ratio N and which is supplied with first and second modulation signals at first and second sections through first and second adders, first and second gain control circuits are provided on input lines of the first and the second modulation signals, respectively. The first gain control circuit has a first gain adjusted to be in inverse proportion to the frequency division ratio N while the second gain control circuit has a second gain adjusted to be in inverse proportion to the gain Kv. Preferably, the first adder is connected between the phase comparator and the loop filter while the second adder is connected between the loop filter and the voltage controlled oscillator.