Abstract: Systems, methods, non-transitory computer-readable media for dynamically estimating interference compensation thresholds for read operations in non-volatile memory devices, including determining a plurality of interference states with respect to an interference source of a target row of a non-volatile memory to be read, determining compensation shifts for the plurality of interference states by determining a compensation shift for each of two or more interference states of the plurality of interference states, and applying the compensation shifts for the plurality of interference states to reading the target row.

Abstract: A memory system includes a semiconductor memory including a plurality of first memory cells each configured to store data in a non-volatile manner according to a threshold voltage, and a controller. The controller is configured to perform a first error correction process for the plurality of first memory cells, based on first hard bit data and first soft bit data acquired using a plurality of first soft bit voltages that have been calculated based on a shift voltage, and to correct the shift voltage when a condition based on correction data generated during the first error correction process, is satisfied.

Abstract: A memory circuit includes a plurality of storage areas each designated by one of a plurality of addresses. The control circuit stores a plurality of values, all of which are different from each other, in the plurality of storage areas, generates a first random number, obtains a first address that is one of the plurality of addresses using the first random number, reads a first value stored in a first storage area designated by the first address, and reads a second value stored in a second storage area designated by a second address. The second address is an address having the largest value among a range of addresses from which the first address can be obtained. The control circuit writes the second value into the first storage area after reading the first value therefrom. The control circuit outputs the first value as one value of an output random number.

Abstract: Systems, methods, non-transitory computer-readable media for dynamically estimating interference compensation thresholds for read operations in non-volatile memory devices, including determining a plurality of interference states with respect to an interference source of a target row of a non-volatile memory to be read, determining compensation shifts for the plurality of interference states by determining a compensation shift for each of two or more interference states of the plurality of interference states, and applying the compensation shifts for the plurality of interference states to reading the target row.

Abstract: According to one embodiment, a memory system includes first and second memory cells and a controller. The controller obtains first and second data based on a first read operation from the first and second memory cells, respectively. The controller obtains third and fourth data based on a second read from the first and second memory cells, respectively. The second read operation is different from the first read operation in a read voltage. The controller sets first and second values indicating likelihood of data stored in the first and second memory cells, respectively, based on information indicating locations of the first and second memory cells. The controller performs error correction on data read from the first and second memory cells using at least the third data and the first value, and using at least fourth data and the second value, respectively.

Abstract: A memory system includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.

Abstract: Systems, methods, non-transitory computer-readable media for dynamically estimating interference compensation thresholds for read operations in non-volatile memory devices, including determining a plurality of interference states with respect to an interference source of a target row of a non-volatile memory to be read, determining compensation shifts for the plurality of interference states by determining a compensation shift for each of two or more interference states of the plurality of interference states, and applying the compensation shifts for the plurality of interference states to reading the target row.

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

Abstract: A memory system includes a semiconductor memory device including a plurality of memory cells each configured to store data in a non-volatile manner according to a threshold voltage thereof and connected to a word line, and a controller configured to perform an error correction based on hard bit data and soft bit data read from the plurality of memory cells, generate a first table based on corrected data, determine a voltage difference between a first voltage and a second voltage, the first voltage being a voltage applied to the word line when the data being corrected is read, and correct the first table based on the voltage difference.

Abstract: A memory system includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.

Abstract: According to one embodiment, a memory system includes first and second memory cells and a controller. The controller obtains first and second data based on a first read operation from the first and second memory cells, respectively. The controller obtains third and fourth data based on a second read from the first and second memory cells, respectively. The second read operation is different from the first read operation in a read voltage. The controller sets first and second values indicating likelihood of data stored in the first and second memory cells, respectively, based on information indicating locations of the first and second memory cells. The controller performs error correction on data read from the first and second memory cells using at least the third data and the first value, and using at least fourth data and the second value, respectively.

Abstract: A memory system includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

Abstract: According to one embodiment, a decoding device comprises a converter configured to convert read data to first likelihood information by using a first conversion table, a decoder which decodes the first likelihood information, a controller which outputs a decoding result of the decoder when the decoder succeeds decoding, and a creator module which creates a second conversion table based on the decoding result when the decoder fails decoding. When the second conversion table is created, at least a part of the decoding result is converted to second likelihood information by using the second conversion table the second likelihood information is decoded.

Abstract: A memory system in an embodiment includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.

Abstract: According to one embodiment, a decoding device comprises a converter configured to convert read data to first likelihood information by using a first conversion table, a decoder which decodes the first likelihood information, a controller which outputs a decoding result of the decoder when the decoder succeeds decoding, and a creator module which creates a second conversion table based on the decoding result when the decoder fails decoding. When the second conversion table is created, at least a part of the decoding result is converted to second likelihood information by using the second conversion table the second likelihood information is decoded.

Abstract: A memory system according to an embodiment includes a semiconductor memory and a memory controller. The semiconductor memory includes memory cells and a sequencer. Each of the memory cells stores first data when it has a first threshold voltage, and stores second data when it has a second threshold voltage. The sequencer performs a first write operation for write data. In the first write operation, the sequencer executes a program loop repeatedly and terminates the first write operation, when the verify operation for the first data has passed and the verify operation for the second data has not passed. The sequencer performs a second write operation for the write data based on a first command from the memory controller after the first write operation is terminated.

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a first latch circuit; and a second latch circuit. The first latch circuit and the second latch circuit are associated with the first memory cell. When the semiconductor memory device receives, from an external device, a first address designating one of the first latch circuit and the second latch circuit and a read command for data of the first memory cell, data is read from the first memory cell and the read data is held in the one of the first latch circuit and the second latch circuit corresponding to the first address.