Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and at least one columnar member. The stacked body is provided on the substrate. In the stacked body, a plurality of insulating films and a plurality of electrode films are layered together alternately. The semiconductor pillar is provided in the stacked body and extends in a stacking direction of the stacked body. The charge storage film is provided between the semiconductor pillar and the stacked body. The columnar member is provided in the stacked body and extends in the stacking direction. A lower portion of the columnar member is provided in the substrate.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and at least one columnar member. The stacked body is provided on the substrate. In the stacked body, a plurality of insulating films and a plurality of electrode films are layered together alternately. The semiconductor pillar is provided in the stacked body and extends in a stacking direction of the stacked body. The charge storage film is provided between the semiconductor pillar and the stacked body. The columnar member is provided in the stacked body and extends in the stacking direction. A lower portion of the columnar member is provided in the substrate.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and at least one columnar member. The stacked body is provided on the substrate. In the stacked body, a plurality of insulating films and a plurality of electrode films are layered together alternately. The semiconductor pillar is provided in the stacked body and extends in a stacking direction of the stacked body. The charge storage film is provided between the semiconductor pillar and the stacked body. The columnar member is provided in the stacked body and extends in the stacking direction. A lower portion of the columnar member is provided in the substrate.

Abstract: An embodiment comprises: a plurality of stacked bodies, each of the stacked bodies including a plurality of control gate electrodes stacked in a first direction, the stacked bodies extending in a second direction intersecting the first direction; an insulating isolation layer disposed between a pair of the stacked bodies adjacent in a third direction intersecting the first direction and the second direction, the insulating isolation layer extending in the second direction; a plurality of semiconductor layers, each of the semiconductor layers extending in the first direction and having its side surface covered by the plurality of control gate electrodes, the semiconductor layers being disposed in a plurality of columns in one of the plurality of stacked bodies; a memory cell disposed between the control gate electrode and the semiconductor layer, the memory cell including a charge accumulation layer; a plurality of bit lines each connected to one end of the semiconductor layer, the bit lines extending in the t

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and at least one columnar member. The stacked body is provided on the substrate. In the stacked body, a plurality of insulating films and a plurality of electrode films are layered together alternately. The semiconductor pillar is provided in the stacked body and extends in a stacking direction of the stacked body. The charge storage film is provided between the semiconductor pillar and the stacked body. The columnar member is provided in the stacked body and extends in the stacking direction. A lower portion of the columnar member is provided in the substrate.

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array includes a plurality of memory cell layers that are stacked. Each memory cell layer comprises a plurality of memory cells formed on a semiconductor layer. The plurality of memory cell layers include: a first memory cell layer where the semiconductor layer is configured of monocrystalline silicon; and a second memory cell layer where the semiconductor layer is configured of polycrystalline silicon. The control circuit, when controlling write or read of data to/from a memory cell belonging to the first memory cell layer, performs control based on a first parameter, and when controlling write or read of data to/from a memory cell belonging to the second memory cell layer, performs control based on a second parameter that differs from the first parameter.

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array includes a plurality of memory cell layers that are stacked. Each memory cell layer comprises a plurality of memory cells formed on a semiconductor layer. The plurality of memory cell layers include: a first memory cell layer where the semiconductor layer is configured of monocrystalline silicon; and a second memory cell layer where the semiconductor layer is configured of polycrystalline silicon. The control circuit, when controlling write or read of data to/from a memory cell belonging to the first memory cell layer, performs control based on a first parameter, and when controlling write or read of data to/from a memory cell belonging to the second memory cell layer, performs control based on a second parameter that differs from the first parameter.

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array includes a plurality of memory cell layers that are stacked. Each memory cell layer comprises a plurality of memory cells formed on a semiconductor layer. The plurality of memory cell layers include: a first memory cell layer where the semiconductor layer is configured of monocrystalline silicon; and a second memory cell layer where the semiconductor layer is configured of polycrystalline silicon. The control circuit, when controlling write or read of data to/from a memory cell belonging to the first memory cell layer, performs control based on a first parameter, and when controlling write or read of data to/from a memory cell belonging to the second memory cell layer, performs control based on a second parameter that differs from the first parameter.

Abstract: A control circuit performs a write operation to 1-page memory cells along the selected word line, by applying a write pulse voltage to a selected word line, and then performs a verify read operation of confirming whether the data write is completed. When the data write is not completed, a step-up operation is performed of raising the write pulse voltage by a certain step-up voltage. A bit scan circuit determines whether the number of memory cells determined to reach a certain threshold voltage is equal to or more than a certain number among the memory cells read at the same time, according to read data held in the sense amplifier circuit as a result of the verify read operation. The control circuit changes the amount of the step-up voltage according to the determination of the bit scan circuit.

Abstract: A semiconductor storage device has a memory cell array including memory cells and a plurality of redundancy regions arranged in a first direction including flag cells, plural word lines extending in the first direction, and plural bit lines extending in a second direction crossing the first direction, and a controller configured to control writing of data to the memory cells and also to the flag cells.

Abstract: According to one embodiment, a semiconductor device comprises an active area extending in a first direction, a contact plug located on a first portion of the active area, and a transistor located on a second portion adjacent to the first portion of the active area in the first direction. A width of a top surface area of the first portion in a second direction perpendicular to the first direction is smaller than that of a top surface area of the second portion in the second direction.

Abstract: According to one embodiment, a semiconductor device comprises an active area extending in a first direction, a contact plug located on a first portion of the active area, and a transistor located on a second portion adjacent to the first portion of the active area in the first direction. A width of a top surface area of the first portion in a second direction perpendicular to the first direction is smaller than that of a top surface area of the second portion in the second direction.

Abstract: In some embodiments, an insulated gate bipolar transistor includes a drift layer, insulation gates formed at a principle surface portion of the drift layer, base regions formed in a between-gate region, an emitter region formed in the base region so as to be adjacent to the insulation gate, an emitter electrode connected to the emitter region, a collector layer formed at the other side of the principle surface portion of the drift layer, and a collector electrode connected to the collector layer. The conductive type base regions are separated with each other by the drift layers, and the drift layer and the emitter electrode are insulated by an interlayer insulation film.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a first sense amplifier circuit, and a second sense amplifier circuit. The memory cell array includes a plurality of first memory cell units, a plurality of second memory cell units, a plurality of first interconnects, and a plurality of second interconnects. The first sense amplifier circuit is connected to the plurality of first interconnects. The second sense amplifier circuit is connected to the plurality of second interconnects. Heights of upper surfaces of interconnects are equal.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of gate electrode structures formed on a semiconductor substrate and an insulating film which covers the gate electrode structures and has an air gap in it. Each of the gate electrode structures includes a gate insulting film, a charge storage layer, an intermediary insulating film, and a control gate electrode. The control gate electrode includes a first control gate and a second control gate whose width is greater than that of the first control gate. The air gap is formed so as to be higher than a space between the control gate electrodes and than the control gate electrodes.

Abstract: According to one embodiment, a semiconductor device comprises an active area extending in a first direction, a contact plug located on a first portion of the active area, and a transistor located on a second portion adjacent to the first portion of the active area in the first direction. A width of a top surface area of the first portion in a second direction perpendicular to the first direction is smaller than that of a top surface area of the second portion in the second direction.

Abstract: A control circuit is configured to perform, in a write operation to a memory cell and a verify operation for verifying a threshold voltage of the memory cell, a voltage control to provide the memory cell with threshold voltage distributions. The circuit is configured to apply, in a read operation from the memory cell, to a selected memory cell a read voltage between the lower and upper limits of the threshold voltage distributions, and apply to an unselected memory cell a first read-pass voltage higher than the upper limit of a first threshold voltage distribution that is the maximum distribution of the threshold voltage distributions.

Abstract: A control circuit performs a write operation to 1-page memory cells along the selected word line, by applying a write pulse voltage to a selected word line, and then performs a verify read operation of confirming whether the data write is completed. When the data write is not completed, a step-up operation is performed of raising the write pulse voltage by a certain step-up voltage. A bit scan circuit determines whether the number of memory cells determined to reach a certain threshold voltage is equal to or more than a certain number among the memory cells read at the same time, according to read data held in the sense amplifier circuit as a result of the verify read operation. The control circuit changes the amount of the step-up voltage according to the determination of the bit scan circuit.

Abstract: A semiconductor memory device includes a first insulation film, Charge accumulation portions, a second insulation film, and a control gate. The first insulation film is located on an active area (AA). The charge accumulation portions comprise minute crystals arranged on the first insulation film. A density of the charge accumulation portions at an end portion in an AA width direction of the first insulation film is higher than a density of the charge accumulation portions at a central potion in the AA width direction. The second insulation film is located on the first insulation film so as to coat the charge accumulation portions. The control gate is located on the second insulation film.

Abstract: According to one embodiment, a semiconductor device comprises an active area extending in a first direction, a contact plug located on a first portion of the active area, and a transistor located on a second portion adjacent to the first portion of the active area in the first direction. A width of a top surface area of the first portion in a second direction perpendicular to the first direction is smaller than that of a top surface area of the second portion in the second direction.